<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/display/dc/dio, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2026-03-04T12:19:49Z</updated>
<entry>
<title>drm/amd/display: Add USB-C DP Alt Mode lane limitation in DCN32</title>
<updated>2026-03-04T12:19:49Z</updated>
<author>
<name>LinCheng Ku</name>
<email>lincheng.ku@amd.com</email>
</author>
<published>2025-12-03T02:18:16Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7df6fe98b24de25010ed22e4f6f90bf869290248'/>
<id>urn:sha1:7df6fe98b24de25010ed22e4f6f90bf869290248</id>
<content type='text'>
[ Upstream commit cea573a8e1ed83840a2173d153dd68e172849d44 ]

[Why]
USB-C DisplayPort Alt Mode with concurrent USB data needs lane count
limitation to prevent incorrect 4-lane DP configuration when only 2 lanes
are available due to hardware lane sharing between DP and USB3.

[How]
Query DMUB for Alt Mode status (is_dp_alt_disable, is_usb, is_dp4) in
dcn32_link_encoder_get_max_link_cap() and cap DP to 2 lanes when USB is
active on USB-C port. Added inline documentation explaining the USB-C
lane sharing constraint.

Reviewed-by: PeiChen Huang &lt;peichen.huang@amd.com&gt;
Signed-off-by: LinCheng Ku &lt;lincheng.ku@amd.com&gt;
Signed-off-by: Chenyu Chen &lt;chen-yu.chen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Rename header file link.h to link_service.h</title>
<updated>2025-09-15T20:57:29Z</updated>
<author>
<name>Wesley Chalmers</name>
<email>Wesley.Chalmers@amd.com</email>
</author>
<published>2025-09-03T01:47:39Z</published>
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<id>urn:sha1:782f0bb5a129f588dc16ad54a2e88c93ef2e079a</id>
<content type='text'>
[WHY]
Header file name "link.h" collides with system header when dc is
compiled as a user-mode library

[WHAT]
Rename link.h to link_service.h to avoid name collision

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove redundant ternary operators</title>
<updated>2025-09-05T21:38:39Z</updated>
<author>
<name>Liao Yuanhong</name>
<email>liaoyuanhong@vivo.com</email>
</author>
<published>2025-09-04T07:10:15Z</published>
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<id>urn:sha1:53c271b9a06ca307c2ce6994877d8d084d031962</id>
<content type='text'>
For ternary operators in the form of "a ? true : false" or
"a ? false : true", if 'a' itself returns a boolean result, the ternary
operator can be omitted. Remove redundant ternary operators to clean up the
code.

Signed-off-by: Liao Yuanhong &lt;liaoyuanhong@vivo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: misc for dio encoder refactor</title>
<updated>2025-03-05T15:39:20Z</updated>
<author>
<name>Peichen Huang</name>
<email>PeiChen.Huang@amd.com</email>
</author>
<published>2025-02-11T06:41:11Z</published>
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<id>urn:sha1:54743ca151a0050e0e9fd89a562392ddbaef4330</id>
<content type='text'>
[WHY]
These are left required changes for dio encoder refactor.

[HOW]
1. original logic is separated by config option
2. new link encoder dp enable/disable code for dcn35
3. process fec only for DP 8b10b encoding

Reviewed-by: Cruise Hung &lt;cruise.hung@amd.com&gt;
Signed-off-by: Peichen Huang &lt;PeiChen.Huang@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor DCN4x and related code</title>
<updated>2025-02-25T16:44:02Z</updated>
<author>
<name>Patel, Swapnil</name>
<email>Swapnil.Patel@amd.com</email>
</author>
<published>2025-02-09T16:42:23Z</published>
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<id>urn:sha1:02a2793ab27e3aa3f345f4e7761005e5c9e3ebd4</id>
<content type='text'>
[why &amp; how]
Refactor existing code related to DCN4x for better code sharing with
other modules.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Swapnil Patel &lt;Swapnil.Patel@amd.com&gt;
Signed-off-by: Zaeem Mohamed &lt;zaeem.mohamed@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix BT2020 YCbCr limited/full range input</title>
<updated>2025-02-19T20:14:10Z</updated>
<author>
<name>Ilya Bakoulin</name>
<email>Ilya.Bakoulin@amd.com</email>
</author>
<published>2025-01-29T19:46:27Z</published>
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<id>urn:sha1:07bc2dcbcf403d47d6f305ef7f0d3d489491c5fb</id>
<content type='text'>
[Why]
BT2020 YCbCr input is not handled properly when full range
quantization is used and limited range is not supported at all.

[How]
- Add enums for BT2020 YCbCr limited/full range
- Add limited range CSC matrix

Reviewed-by: Krunoslav Kovac &lt;krunoslav.kovac@amd.com&gt;
Signed-off-by: Ilya Bakoulin &lt;Ilya.Bakoulin@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Robert Mader &lt;robert.mader@collabora.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Allow reuse of of DCN4x code</title>
<updated>2025-02-13T02:03:01Z</updated>
<author>
<name>Dmytro</name>
<email>dmytro.laktyushkin@amd.com</email>
</author>
<published>2024-10-25T14:31:18Z</published>
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<id>urn:sha1:2739bd123782f9bedc39285b3965ff2b4b3e6411</id>
<content type='text'>
Remove the static qualifier to make it available for code sharing
with other components.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Dmytro &lt;dmytro.laktyushkin@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: improve dpia pre-train</title>
<updated>2025-01-10T17:12:29Z</updated>
<author>
<name>Peichen Huang</name>
<email>PeiChen.Huang@amd.com</email>
</author>
<published>2024-12-25T07:51:34Z</published>
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<id>urn:sha1:230dced3e2b712017c03ce0afb3f8c48d8af20ee</id>
<content type='text'>
[WHY]
We see unstable DP LL 4.2.1.3 test result with dpia pre-train. It is
because the outbox interrupt mechanism can not handle HPD
immediately and require some improvement.

[HOW]
1. not enable link if hpd_pending is true.
2. abort pre-train if training failed and hpd_pending is true.
3. check if 2 lane supported when it is alt mode

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Reviewed-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Signed-off-by: Peichen Huang &lt;PeiChen.Huang@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: have pretrain for dpia</title>
<updated>2025-01-06T19:44:27Z</updated>
<author>
<name>Peichen Huang</name>
<email>PeiChen.Huang@amd.com</email>
</author>
<published>2024-12-04T07:20:10Z</published>
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<id>urn:sha1:44063dbcdbd8abf172b8cc30e18d7e2948e9d699</id>
<content type='text'>
[WHY]
We like to have pretrain for dpia link so that dp and dp tunneling
have aligned behavior. The Main difficult for dpia pretrain is that
encoder can not get corresponded dpia port when link detection
in current implementation.

[HOW]
1. create enable/disable dpia output functions for dcn35 encoder
and have dpia_id and other necessary info as inputs.
2. dcn35 dpia use the new functions to enable/disable output.
3. have a option to enable/disable the change.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Reviewed-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Signed-off-by: Peichen Huang &lt;PeiChen.Huang@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove useless assignments and variables</title>
<updated>2024-10-28T20:36:13Z</updated>
<author>
<name>Alex Hung</name>
<email>alex.hung@amd.com</email>
</author>
<published>2024-10-16T18:18:39Z</published>
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<id>urn:sha1:b0814fa3be76a8c62cbb9e02bb851b0ec234037d</id>
<content type='text'>
[WHAT &amp; HOW]
misc0, temp and split_pipe are assigned but immediately re-assigned
to other values. The early assignments are useless and are removed.
Unused variables are removed as well.

This fixes 5 UNUSED_VALUE issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
