<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/display/dc/dcn30, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2026-02-19T15:31:33Z</updated>
<entry>
<title>drm/amd/display: extend delta clamping logic to CM3 LUT helper</title>
<updated>2026-02-19T15:31:33Z</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2025-12-08T23:44:15Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8e6f50396170939e4444ae18cd488f24b41bd5fd'/>
<id>urn:sha1:8e6f50396170939e4444ae18cd488f24b41bd5fd</id>
<content type='text'>
[ Upstream commit d25b32aa829a3ed5570138e541a71fb7805faec3 ]

Commit 27fc10d1095f ("drm/amd/display: Fix the delta clamping for shaper
LUT") fixed banding when using plane shaper LUT in DCN10 CM helper.  The
problem is also present in DCN30 CM helper, fix banding by extending the
same bug delta clamping fix to CM3.

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 0274a54897f356f9c78767c4a2a5863f7dde90c6)
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix wrong color value mapping on MCM shaper LUT</title>
<updated>2026-02-11T12:41:58Z</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2026-01-22T15:20:29Z</published>
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<id>urn:sha1:100f3bf91461285f2c155f5e9e883668c85e6627</id>
<content type='text'>
[ Upstream commit 8f959d37c1f2efec6dac55915ee82302e98101fb ]

Some shimmer/colorful points appears when using the steamOS color
pipeline for HDR on gaming with DCN32. These points look like black
values being wrongly mapped to red/blue/green values. It was caused
because the number of hw points in regular LUTs and in a shaper LUT was
treated as the same.

DCN3+ regular LUTs have 257 bases and implicit deltas (i.e. HW
calculates them), but shaper LUT is a special case: it has 256 bases and
256 deltas, as in DCN1-2 regular LUTs, and outputs 14-bit values.

Fix that by setting by decreasing in 1 the number of HW points computed
in the LUT segmentation so that shaper LUT (i.e. fixpoint == true) keeps
the same DCN10 CM logic and regular LUTs go with `hw_points + 1`.

CC: Krunoslav Kovac &lt;Krunoslav.Kovac@amd.com&gt;
Fixes: 4d5fd3d08ea9 ("drm/amd/display: PQ tail accuracy")
Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 5006505b19a2119e71c008044d59f6d753c858b9)
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove unused cm3_helper_translate_curve_to_degamma_hw_format</title>
<updated>2024-11-04T16:26:20Z</updated>
<author>
<name>Dr. David Alan Gilbert</name>
<email>linux@treblig.org</email>
</author>
<published>2024-10-09T00:33:34Z</published>
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<id>urn:sha1:8b89acc0b2baecfe331f5336e7ff1fcc5a44b062</id>
<content type='text'>
cm3_helper_translate_curve_to_degamma_hw_format() since it was added in
2020's commit
03f54d7d3448 ("drm/amd/display: Add DCN3 DPP")

Remove it.

Signed-off-by: Dr. David Alan Gilbert &lt;linux@treblig.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix low black values by increasing error</title>
<updated>2024-10-07T18:12:01Z</updated>
<author>
<name>Peterson</name>
<email>peterson.guo@amd.com</email>
</author>
<published>2024-09-23T14:30:50Z</published>
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<id>urn:sha1:eda7f2e9bb3b6ba16cb19e521b433b22b220c0d0</id>
<content type='text'>
[WHY]
Regamma resolution for the first few black levels can have problems for
calibration.

[HOW]
HW LUT is divided into N power-of-2 regions each with K segments.  For
SDR mode we set min point at 2^-10 and increments of 2^-13. It's
generally more than 8-bit SDR needs, but some calibration tools and API
use 12-bit curves.
The fix shifts starting point to 2^-12 and starting increments at 2^-16.

Reviewed-by: Krunoslav Kovac &lt;krunoslav.kovac@amd.com&gt;
Signed-off-by: Peterson &lt;peterson.guo@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix index out of bounds in DCN30 color transformation</title>
<updated>2024-07-23T21:41:39Z</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2024-07-20T12:35:20Z</published>
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<id>urn:sha1:d81873f9e715b72d4f8d391c8eb243946f784dfc</id>
<content type='text'>
This commit addresses a potential index out of bounds issue in the
`cm3_helper_translate_curve_to_hw_format` function in the DCN30 color
management module. The issue could occur when the index 'i' exceeds the
number of transfer function points (TRANSFER_FUNC_POINTS).

The fix adds a check to ensure 'i' is within bounds before accessing the
transfer function points. If 'i' is out of bounds, the function returns
false to indicate an error.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:180 cm3_helper_translate_curve_to_hw_format() error: buffer overflow 'output_tf-&gt;tf_pts.red' 1025 &lt;= s32max
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:181 cm3_helper_translate_curve_to_hw_format() error: buffer overflow 'output_tf-&gt;tf_pts.green' 1025 &lt;= s32max
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:182 cm3_helper_translate_curve_to_hw_format() error: buffer overflow 'output_tf-&gt;tf_pts.blue' 1025 &lt;= s32max

Cc: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Cc: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Cc: Roman Li &lt;roman.li@amd.com&gt;
Cc: Alex Hung &lt;alex.hung@amd.com&gt;
Cc: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Reviewed-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix index out of bounds in DCN30 degamma hardware format translation</title>
<updated>2024-07-23T21:41:12Z</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2024-07-20T13:14:02Z</published>
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<id>urn:sha1:bc50b614d59990747dd5aeced9ec22f9258991ff</id>
<content type='text'>
This commit addresses a potential index out of bounds issue in the
`cm3_helper_translate_curve_to_degamma_hw_format` function in the DCN30
color  management module. The issue could occur when the index 'i'
exceeds the  number of transfer function points (TRANSFER_FUNC_POINTS).

The fix adds a check to ensure 'i' is within bounds before accessing the
transfer function points. If 'i' is out of bounds, the function returns
false to indicate an error.

Reported by smatch:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:338 cm3_helper_translate_curve_to_degamma_hw_format() error: buffer overflow 'output_tf-&gt;tf_pts.red' 1025 &lt;= s32max
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:339 cm3_helper_translate_curve_to_degamma_hw_format() error: buffer overflow 'output_tf-&gt;tf_pts.green' 1025 &lt;= s32max
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:340 cm3_helper_translate_curve_to_degamma_hw_format() error: buffer overflow 'output_tf-&gt;tf_pts.blue' 1025 &lt;= s32max

Cc: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Cc: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Cc: Roman Li &lt;roman.li@amd.com&gt;
Cc: Alex Hung &lt;alex.hung@amd.com&gt;
Cc: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Reviewed-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactoring HPO</title>
<updated>2024-07-23T21:35:45Z</updated>
<author>
<name>Revalla Hari Krishna</name>
<email>harikrishna.revalla@amd.com</email>
</author>
<published>2024-07-08T10:05:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6fa4bf3dce0668a96faca0024e382f4489a9cc9b'/>
<id>urn:sha1:6fa4bf3dce0668a96faca0024e382f4489a9cc9b</id>
<content type='text'>
[Why]
To refactor HPO files

[How]
Moved hpo related files to specific hpo folder and
update Makefiles.

Reviewed-by: Martin Leung &lt;martin.leung@amd.com&gt;
Signed-off-by: Revalla Hari Krishna &lt;harikrishna.revalla@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactoring DWB related files from dcn30 Files</title>
<updated>2024-07-23T21:07:12Z</updated>
<author>
<name>Mudimela</name>
<email>lmudimel@amd.com</email>
</author>
<published>2024-07-02T06:25:56Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b8d3782da396215615c3d125f0829d1d06ad2c97'/>
<id>urn:sha1:b8d3782da396215615c3d125f0829d1d06ad2c97</id>
<content type='text'>
[Why]
To refactor DWB related files from dcn30 Files

[How]
Moved DWB related files from dcn30 to specific DWB folder and
updated Makefiles to fix Compilation.

Reviewed-by: Martin Leung &lt;martin.leung@amd.com&gt;
Signed-off-by: Jerry Zuo &lt;jerry.zuo@amd.com&gt;
Signed-off-by: Mudimela &lt;lmudimel@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactoring MPC</title>
<updated>2024-07-23T21:07:11Z</updated>
<author>
<name>Mounika Adhuri</name>
<email>moadhuri@amd.com</email>
</author>
<published>2024-06-26T13:21:04Z</published>
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<id>urn:sha1:5ed9481db74740fd33ec4079b29db88e8c9f4a1c</id>
<content type='text'>
[Why]
To refactor MPC files

[How]
Moved MPC files to respective folders and
updated makefiles appropriately.

Reviewed-by: Martin Leung &lt;martin.leung@amd.com&gt;
Signed-off-by: Jerry Zuo &lt;jerry.zuo@amd.com&gt;
Signed-off-by: Mounika Adhuri &lt;moadhuri@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Move dio files into dio folder</title>
<updated>2024-07-01T20:10:35Z</updated>
<author>
<name>Bhuvanachandra Pinninti</name>
<email>bpinnint@amd.com</email>
</author>
<published>2024-06-20T12:24:23Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d19deabe5a4566851f6ecade5ebd2e63c3248cf2'/>
<id>urn:sha1:d19deabe5a4566851f6ecade5ebd2e63c3248cf2</id>
<content type='text'>
[why]
Refactor the code of dio to unit test.

[how]
Moved files to respective folders and changed cMakeLists and makefiles.

Acked-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Jerry Zuo &lt;jerry.zuo@amd.com&gt;
Signed-off-by: Bhuvanachandra Pinninti &lt;bpinnint@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
