kernel/drivers/gpu/drm/amd/display/dc/dce80, branch linux-5.1.y

Merge v5.0 into drm-next

2019-03-04T02:02:55Z

There is a really hairy resolution involving amdgpu fixes, that I'd rather confirm here. Also some misc fixes are landed by me, but the pr has them as well. Signed-off-by: Dave Airlie

drm/amd/display: set clocks to 0 on suspend on dce80

2019-02-20T21:58:06Z

[Why] When a dce80 asic was suspended, the clocks were not set to 0. Upon resume, the new clock was compared to the existing clock, they were found to be the same, and so the clock was not set. This resulted in a blackscreen. [How] In atomic commit, check to see if there are any active pipes. If no, set clocks to 0 Signed-off-by: Bhawanpreet Lakha Reviewed-by: Nicholas Kazlauskas Acked-by: Leo Li Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amd/display: fix optimize_bandwidth func pointer for dce80

2019-02-20T21:57:47Z

[Why] optimize_bandwidth was using dce100_prepare_bandwidth this is incorrect [How] change it to dce100_optimize_bandwidth Signed-off-by: Bhawanpreet Lakha Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amd/display: fix eDP fast bootup for pre-raven asic

2019-01-25T21:15:36Z

[Why] For fastboot, Bios will light up eDP before SW driver is loaded. SW driver will check if eDP is lit by bios through reading the BIOS_SCRATCH_3 register. If lit, SW driver will not power down eDP power and phy to save time. Definition of BIOS_SCRATCH_3 are missing for pre-raven asic. This causes eDP fast boot to not work property. For some eDP panels, even if dp tx sends NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not handle properly. This may cause a short flash on screen. [How] Add definition of BIOS_SCRATCH_3 for all asic Signed-off-by: hersen wu Reviewed-by: Alex Deucher Reviewed-by: Charlene Liu Acked-by: Leo Li Acked-by: Yongqiang Sun Signed-off-by: Alex Deucher

drm/amd/display: Change from aux_engine to dce_aux

2019-01-14T20:40:48Z

[Why] The aux_engine struct is needlessly complex and is defined multiple times. It contains function pointers that each have only one version and are called only from inside dce_aux. [How] Replace aux_engine with a new struct called dce_aux. Remove all function pointers and call functions directly. Remove unused functions Signed-off-by: David Francis Reviewed-by: Harry Wentland Acked-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: Fix 64-bit division for 32-bit builds

2019-01-14T20:04:45Z

[Why] 32-bit builds break when doing 64-bit division directly. [How] Use the div_u64() function instead to perform the division. Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-December/201008.html Signed-off-by: Ken Chalmers Reviewed-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: Use 100 Hz precision for pipe pixel clocks

2019-01-14T20:04:39Z

[Why] Users would like more accurate pixel clocks, especially for fractional "TV" frame rates like 59.94 Hz. [How] Store and communicate pixel clocks with 100 Hz accuracy from dc_crtc_timing through to BIOS command table setpixelclock call. Signed-off-by: Ken Chalmers Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: Remove duplicate header

2018-11-26T20:54:40Z

Remove dce/dce_mem_input.h which is included more than once Signed-off-by: Brajeswar Ghosh Signed-off-by: Alex Deucher

drm/amd/display: rename dccg to clk_mgr

2018-11-05T19:20:48Z

In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: split dccg clock manager into asic folders

2018-11-05T19:20:42Z

Currently dccg contains code related to every dcn revision in a single file. This change splits out the dcn parts of code into correct folders Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher