kernel/drivers/gpu/drm/amd/display/dc/dc.h, branch linux-5.1.y

drm/amd/display: If one stream full updates, full update all planes

2019-04-15T04:45:43Z

[Why] On some compositors, with two monitors attached, VT terminal switch can cause a graphical issue by the following means: There are two streams, one for each monitor. Each stream has one plane current state: M1:S1->P1 M2:S2->P2 The user calls for a terminal switch and a commit is made to change both planes to linear swizzle mode. In atomic check, a new dc_state is constructed with new planes on each stream new state: M1:S1->P3 M2:S2->P4 In commit tail, each stream is committed, one at a time. The first stream (S1) updates properly, triggerring a full update and replacing the state current state: M1:S1->P3 M2:S2->P4 The update for S2 comes in, but dc detects that there is no difference between the stream and plane in the new and current states, and so triggers a fast update. The fast update does not program swizzle, so the second monitor is corrupted [How] Add a flag to dc_plane_state that forces full updates When a stream undergoes a full update, set this flag on all changed planes, then clear it on the current stream Subsequent streams will get full updates as a result Signed-off-by: David Francis Signed-off-by: Nicholas Kazlauskas Reviewed-by: Roman Li Acked-by: Bhawanpreet Lakha Acked-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amd/display: interface to check if timing can be seamless

2019-02-06T18:30:44Z

[Why] Need to figure out whether a timing we want to commit matches something that GOP already programmed, in which case we can decide to some optimizations [How] 1. Add way to check for DIG FE 2. Add way to check for matching OTG timing 3. Add way to check for matching pixel clock (if possible) - Currently only support DP for pixel clock, since it is easy to calc Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: 3.2.17

2019-02-06T18:30:36Z

Signed-off-by: mark mcgarrity Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: DC VM Fixes

2019-02-06T18:30:12Z

[Why] VM_helper needs to be intialized with the dc struct in order to fix an unallocated memory issue. System aperture settings should be initialized to 0 and guarded with a check to make sure vm_config is valid. [How] Allocate and free memory for vm_helper with other dc members. Check whether the vm_config valid bit is set before initializing aperture settings. Signed-off-by: Eryk Brol Reviewed-by: Jun Lei Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: add a debug flag to force odm combine

2019-02-06T02:16:23Z

Adding a bit vector to allow forcing odm on specific otgs Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: 3.2.16

2019-02-06T02:16:23Z

Signed-off-by: Steven Chiu Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: 3.2.15

2019-01-25T21:15:37Z

Signed-off-by: Steven Chiu Reviewed-by: Aric Cyr Acked-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: 3.2.14

2019-01-14T20:42:37Z

Signed-off-by: Steven Chiu Reviewed-by: Yongqiang Sun Acked-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: 3.2.13

2019-01-14T20:40:27Z

Signed-off-by: Steven Chiu Reviewed-by: Yongqiang Sun Acked-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: Set link rate set if eDP ver >= 1.4.

2019-01-14T20:40:08Z

[Why] If eDP ver >= 1.4, the Source device must use LINK_RATE_SET. [How] Get LINK_RATE_SET by reading DPCD 10h-1fh, then write DPCD 00115h before link training. Signed-off-by: Derek Lai Reviewed-by: Tony Cheng Acked-by: Leo Li Signed-off-by: Alex Deucher