<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/display/dc/dc.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-03-14T21:01:14Z</updated>
<entry>
<title>drm/amd/display: clean up dcn pplib notification call</title>
<updated>2018-03-14T21:01:14Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2018-02-16T18:18:59Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=17ac50368f83ead67f9e3c9b9704f927f214da9d'/>
<id>urn:sha1:17ac50368f83ead67f9e3c9b9704f927f214da9d</id>
<content type='text'>
We have unused variables being populated when notifying pplib.
This change amends that.

Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)</title>
<updated>2018-03-14T20:16:34Z</updated>
<author>
<name>Yongqiang Sun</name>
<email>yongqiang.sun@amd.com</email>
</author>
<published>2018-02-28T22:14:50Z</published>
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<id>urn:sha1:45bb8dd696eaff9c96afd2b210f0d8cf5025dd65</id>
<content type='text'>
Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is
higher than maximum dpp clk as per dpm table.
	set dispclk to the value of maximum supported dpp clk
	set div to 1
	set dispclk to request value.
Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is
higher than maximum dpp clk as per dpm table.
	set dispclk to the value of maximum supported dpp clk
	set div to 0
	set dispclk to request value.

v2: squash in !DCN build fix

Signed-off-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dal 3.1.38</title>
<updated>2018-03-14T20:08:47Z</updated>
<author>
<name>Tony Cheng</name>
<email>tony.cheng@amd.com</email>
</author>
<published>2018-02-21T21:41:19Z</published>
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<id>urn:sha1:3f7194bce26ed39055439ebcf608fab43e846f2e</id>
<content type='text'>
Signed-off-by: Tony Cheng &lt;tony.cheng@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add variable refresh rate parameters to DC structures</title>
<updated>2018-03-14T20:08:47Z</updated>
<author>
<name>Anthony Koo</name>
<email>Anthony.Koo@amd.com</email>
</author>
<published>2018-02-28T16:37:51Z</published>
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<id>urn:sha1:64ed6a2eba3cb4146d2ff731293939ae84fad740</id>
<content type='text'>
Time stamping will be part of surface, and will be updated when address is flipped.
FreeSync parameters will be attached to stream, as it adjusts the timing dynamically.

Signed-off-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Varibright fix bug and review comments</title>
<updated>2018-03-14T20:08:42Z</updated>
<author>
<name>SivapiriyanKumarasamy</name>
<email>sivapiriyan.kumarasamy@amd.com</email>
</author>
<published>2018-02-23T18:04:13Z</published>
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<id>urn:sha1:9aef1a31709076660f7d5f638ab5ecadea4ca856</id>
<content type='text'>
Fix bug and make changes from review 132656

Signed-off-by: SivapiriyanKumarasamy &lt;sivapiriyan.kumarasamy@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Vari-bright looks disabled near end of MM14</title>
<updated>2018-03-14T20:08:41Z</updated>
<author>
<name>SivapiriyanKumarasamy</name>
<email>sivapiriyan.kumarasamy@amd.com</email>
</author>
<published>2018-02-13T22:37:23Z</published>
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<id>urn:sha1:aa5a5777304228819a52562d346bc3eb1b4873fa</id>
<content type='text'>
Avoid hanging DMCU by setting abm level only when OTG unblanked

Signed-off-by: SivapiriyanKumarasamy &lt;sivapiriyan.kumarasamy@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Return success when enabling interrupt</title>
<updated>2018-03-05T20:35:59Z</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2018-02-13T16:03:01Z</published>
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<id>urn:sha1:a0e30392dd03727c069d1cf93ee6582473dd3dd6</id>
<content type='text'>
Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dal 3.1.37</title>
<updated>2018-03-05T20:35:47Z</updated>
<author>
<name>Tony Cheng</name>
<email>tony.cheng@amd.com</email>
</author>
<published>2018-02-21T21:40:50Z</published>
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<id>urn:sha1:5dd0bb34edc160cf725f8e00e3bc3c8be883842e</id>
<content type='text'>
Signed-off-by: Tony Cheng &lt;tony.cheng@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dal 3.1.36</title>
<updated>2018-03-05T20:34:46Z</updated>
<author>
<name>Tony Cheng</name>
<email>Tony.Cheng@amd.com</email>
</author>
<published>2018-02-17T06:34:42Z</published>
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<id>urn:sha1:c1d8ba6e0a1c34811afe7f881207062227d81872</id>
<content type='text'>
Signed-off-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add diags clock programming</title>
<updated>2018-03-05T20:34:40Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2018-02-13T19:41:51Z</published>
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<id>urn:sha1:15cf3974eb06e7b6be1f8f02581759b5f3d9f1e4</id>
<content type='text'>
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
