<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/display/dc/bios, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-02-18T23:01:00Z</updated>
<entry>
<title>drm/amd/display/dc/bios_parser2: Mark expected switch fall-throughs</title>
<updated>2019-02-18T23:01:00Z</updated>
<author>
<name>Gustavo A. R. Silva</name>
<email>gustavo@embeddedor.com</email>
</author>
<published>2019-02-15T16:50:23Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7ac65f42769f93d74c0b68ef1b054e01b971dba1'/>
<id>urn:sha1:7ac65f42769f93d74c0b68ef1b054e01b971dba1</id>
<content type='text'>
In preparation to enabling -Wimplicit-fallthrough, mark switch
cases where we are expecting to fall through.

Warning level 3 was used: -Wimplicit-fallthrough=3

This patch is part of the ongoing efforts to enable
-Wimplicit-fallthrough.

Signed-off-by: Gustavo A. R. Silva &lt;gustavo@embeddedor.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Connect dig_fe to otg directly instead of calling bios</title>
<updated>2019-01-25T21:15:37Z</updated>
<author>
<name>hersen wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2019-01-11T17:43:20Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d2c460e7537f003e5bfb1a94c9201bcbeca6949f'/>
<id>urn:sha1:d2c460e7537f003e5bfb1a94c9201bcbeca6949f</id>
<content type='text'>
[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other fmt register
for bios usage which is redundancy and uncessary.

[How] Program dig_soruce_select register directly

Signed-off-by: hersen wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>revert "drm/amd/display: Add condition to sync eDP SW status and HW status"</title>
<updated>2019-01-25T21:15:37Z</updated>
<author>
<name>Eric Yang</name>
<email>Eric.Yang2@amd.com</email>
</author>
<published>2019-01-11T21:54:05Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8635c5a784105af8b833c43bf22cbabd6e64a8f1'/>
<id>urn:sha1:8635c5a784105af8b833c43bf22cbabd6e64a8f1</id>
<content type='text'>
[Why]
This change causes regression for S4 resume where gamma is not
programmed. The change incorrectly updates the requested dpms_off
state.

This reverts commit d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600.

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix eDP fast bootup for pre-raven asic</title>
<updated>2019-01-25T21:15:36Z</updated>
<author>
<name>hersen wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2019-01-11T15:39:30Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c69dffab819f5abd98f9791fdb8aede1ec2f172f'/>
<id>urn:sha1:c69dffab819f5abd98f9791fdb8aede1ec2f172f</id>
<content type='text'>
[Why]
For fastboot, Bios will light up eDP before SW driver is loaded. SW
driver will check if eDP is lit by bios through reading the
BIOS_SCRATCH_3 register. If lit, SW driver will not power down eDP
power and phy to save time.

Definition of BIOS_SCRATCH_3 are missing for pre-raven asic. This
causes eDP fast boot to not work property. For some eDP panels, even
if dp tx sends NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not
handle properly. This may cause a short flash on screen.

[How] Add definition of BIOS_SCRATCH_3 for all asic

Signed-off-by: hersen wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Acked-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Expand set_pixel_clock debug log message</title>
<updated>2019-01-14T20:04:45Z</updated>
<author>
<name>Ken Chalmers</name>
<email>ken.chalmers@amd.com</email>
</author>
<published>2018-11-05T16:34:57Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b187af3709131f0530995b1abb9da4c18026417b'/>
<id>urn:sha1:b187af3709131f0530995b1abb9da4c18026417b</id>
<content type='text'>
[Why]
For more informative debugging.

[How]
Add timing generator and PLL ids to output, to make it clear which pixel
clock is being set.

Signed-off-by: Ken Chalmers &lt;ken.chalmers@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Use 100 Hz precision for pipe pixel clocks</title>
<updated>2019-01-14T20:04:39Z</updated>
<author>
<name>Ken Chalmers</name>
<email>ken.chalmers@amd.com</email>
</author>
<published>2018-11-06T19:24:12Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=380604e27bc9c26ce64a83044aa1ea76ffd28caf'/>
<id>urn:sha1:380604e27bc9c26ce64a83044aa1ea76ffd28caf</id>
<content type='text'>
[Why]
Users would like more accurate pixel clocks, especially for fractional
"TV" frame rates like 59.94 Hz.

[How]
Store and communicate pixel clocks with 100 Hz accuracy from
dc_crtc_timing through to BIOS command table setpixelclock call.

Signed-off-by: Ken Chalmers &lt;ken.chalmers@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add functionality to get XGMI SS info</title>
<updated>2018-12-18T22:39:56Z</updated>
<author>
<name>Leo Li</name>
<email>sunpeng.li@amd.com</email>
</author>
<published>2018-10-31T21:07:41Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1c01a45a86ed6991953e74be63b6a7e33b387954'/>
<id>urn:sha1:1c01a45a86ed6991953e74be63b6a7e33b387954</id>
<content type='text'>
[Why]
When XGMI is enabled, the DP reference clock needs to be adjusted
according to the XGMI spread spectrum percentage and mode. But first,
we need the ability to fetch this info.

[How]
Within the BIOS parser, Read from vBIOS when XGMI SS info is requested.

In addition, diags build uses include_legacy/atomfirmware.h for the
smu_info_v3_3 table headers. Update that as well.

Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCE_VERSION_12_1 enum for Vega 20</title>
<updated>2018-12-18T22:39:49Z</updated>
<author>
<name>Leo Li</name>
<email>sunpeng.li@amd.com</email>
</author>
<published>2018-10-31T20:56:54Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b8b6ce89016485cb92fdf2f527b40249aefbc470'/>
<id>urn:sha1:b8b6ce89016485cb92fdf2f527b40249aefbc470</id>
<content type='text'>
[Why]
We'll need a way to differentiate Vega 20 in DC

[How]
Add a DCE_VERSION_12_1 enum, which will be returned as the DC version if
the ASIC used is a Vega 20.

Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Reviewed-by: David Francis &lt;David.Francis@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add condition to sync eDP SW status and HW status</title>
<updated>2018-11-05T19:21:45Z</updated>
<author>
<name>Lewis Huang</name>
<email>Lewis.Huang@amd.com</email>
</author>
<published>2018-10-18T09:52:19Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600'/>
<id>urn:sha1:d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600</id>
<content type='text'>
[Why]
Need to disable EDP backlight when enter S4 with EDP only
and resume from S4 with secondary only.

[How]
Align the real hw and sw state via vBios scratch register in
function enable_accelerated_mode when resume from S4.

Signed-off-by: Lewis Huang &lt;Lewis.Huang@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix up coverity issues</title>
<updated>2018-11-05T19:21:35Z</updated>
<author>
<name>Aric Cyr</name>
<email>aric.cyr@amd.com</email>
</author>
<published>2018-10-10T23:02:48Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=69133b89359120e741dff3e09dcfdc08ff954445'/>
<id>urn:sha1:69133b89359120e741dff3e09dcfdc08ff954445</id>
<content type='text'>
[Why]
Coverity found various high-impact issues that need resolving.

[How]
Fix  some buffer overruns and uninitialized variables.

Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
