<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2017-12-27T16:34:02Z</updated>
<entry>
<title>drm/amdgpu: rename vm_id to vmid</title>
<updated>2017-12-27T16:34:02Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-12-18T16:08:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c4f46f22c448ff571eb8fdbe4ab71a25805228d1'/>
<id>urn:sha1:c4f46f22c448ff571eb8fdbe4ab71a25805228d1</id>
<content type='text'>
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: allow harvesting check for Polaris VCE</title>
<updated>2017-11-02T03:37:16Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-11-01T01:12:35Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=32bec2afa525149288e6696079bc85f747fa2138'/>
<id>urn:sha1:32bec2afa525149288e6696079bc85f747fa2138</id>
<content type='text'>
Fixes init failures on Polaris cards with harvested
VCE blocks.

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Program ring for vce instance 1 at its register space</title>
<updated>2017-05-31T17:09:15Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-05-29T17:13:59Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=45cc6586b7a73e84a8806881122b6ec306cdc9e7'/>
<id>urn:sha1:45cc6586b7a73e84a8806881122b6ec306cdc9e7</id>
<content type='text'>
We need program ring buffer on instance 1 register space domain,
when only if instance 1 available, with two instances or instance 0,
and we need only program instance 0 regsiter space domain for ring.

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: various cleanups for uvd/vce.</title>
<updated>2017-04-04T17:40:33Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-03-30T07:45:52Z</published>
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<id>urn:sha1:502372878af1caa0b3050b0820ef112a5b8adf6b</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add a new register define for APU in VI.</title>
<updated>2017-03-30T03:54:06Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-03-17T08:21:55Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1c622002b1aae6bf97be6f3c36203a61d8cc61cb'/>
<id>urn:sha1:1c622002b1aae6bf97be6f3c36203a61d8cc61cb</id>
<content type='text'>
the ixcurrent_pg_status addr is different between APU and DGPU.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: refine vce_3.0 code.</title>
<updated>2017-03-30T03:53:51Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-03-13T08:05:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=2667989927bfb419d854169d845f205a69de423a'/>
<id>urn:sha1:2667989927bfb419d854169d845f205a69de423a</id>
<content type='text'>
fix logic error in hw_fini and
set_clockgating_state functions.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/ih: store the full context id</title>
<updated>2017-03-30T03:53:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-11-29T23:02:12Z</published>
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<id>urn:sha1:7ccf5aa8ba8241cba0f6a894ec1e68a2794cef6f</id>
<content type='text'>
The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics.  Expand the
src_id field to handle this.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch ih handling to two levels (v3)</title>
<updated>2017-03-30T03:53:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-03-29T22:28:50Z</published>
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<id>urn:sha1:d766e6a393383c60a55bdcc72586f21a1ff12509</id>
<content type='text'>
Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: change wptr to 64 bits (v2)</title>
<updated>2017-03-30T03:53:35Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-03-12T01:32:30Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=536fbf946cf84ff60cdef471c23ab96058e62f39'/>
<id>urn:sha1:536fbf946cf84ff60cdef471c23ab96058e62f39</id>
<content type='text'>
Newer asics need 64 bit wptrs.  If the wptr is now
smaller than the rptr that doesn't indicate a wrap-around
anymore.

v2: integrate Christian's comments.

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: read hw register to check pg status.</title>
<updated>2017-02-13T17:43:04Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-02-08T09:17:55Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=254cd2e08dd0c44f9de6424f10390343a34b4f5a'/>
<id>urn:sha1:254cd2e08dd0c44f9de6424f10390343a34b4f5a</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
