<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2017-04-04T17:40:33Z</updated>
<entry>
<title>drm/amdgpu: various cleanups for uvd/vce.</title>
<updated>2017-04-04T17:40:33Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-03-30T07:45:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=502372878af1caa0b3050b0820ef112a5b8adf6b'/>
<id>urn:sha1:502372878af1caa0b3050b0820ef112a5b8adf6b</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove redundant outer loop and remove commented out code</title>
<updated>2017-03-30T03:54:04Z</updated>
<author>
<name>Colin Ian King</name>
<email>colin.king@canonical.com</email>
</author>
<published>2017-03-17T14:37:22Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f917c2ad92c416b05d876f513a9963a6f5ed139d'/>
<id>urn:sha1:f917c2ad92c416b05d876f513a9963a6f5ed139d</id>
<content type='text'>
The outer loop is redundant and can be removed as it is doing nothing
useful. Also remove some commented out code that is not being used.

Detected by CoverityScan, CID#1402073

Signed-off-by: Colin Ian King &lt;colin.king@canonical.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/ih: store the full context id</title>
<updated>2017-03-30T03:53:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-11-29T23:02:12Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7ccf5aa8ba8241cba0f6a894ec1e68a2794cef6f'/>
<id>urn:sha1:7ccf5aa8ba8241cba0f6a894ec1e68a2794cef6f</id>
<content type='text'>
The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics.  Expand the
src_id field to handle this.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch ih handling to two levels (v3)</title>
<updated>2017-03-30T03:53:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-03-29T22:28:50Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d766e6a393383c60a55bdcc72586f21a1ff12509'/>
<id>urn:sha1:d766e6a393383c60a55bdcc72586f21a1ff12509</id>
<content type='text'>
Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: change wptr to 64 bits (v2)</title>
<updated>2017-03-30T03:53:35Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-03-12T01:32:30Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=536fbf946cf84ff60cdef471c23ab96058e62f39'/>
<id>urn:sha1:536fbf946cf84ff60cdef471c23ab96058e62f39</id>
<content type='text'>
Newer asics need 64 bit wptrs.  If the wptr is now
smaller than the rptr that doesn't indicate a wrap-around
anymore.

v2: integrate Christian's comments.

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vce2: fix vce bar programming</title>
<updated>2017-03-30T03:53:22Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-02-17T18:50:15Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=dc3abc16a72776ed1b631d27d2e595cbf34f353e'/>
<id>urn:sha1:dc3abc16a72776ed1b631d27d2e595cbf34f353e</id>
<content type='text'>
Program the VCE BAR and offsets properly.  The current code
was carried over from a limitation from older VCE versions.

Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move subfunctions to the front of vce_v2_0.c.</title>
<updated>2017-02-08T22:23:03Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-26T08:46:22Z</published>
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<id>urn:sha1:f1ea278d6fe00945b21ac9f9f56fd424b719bdea</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: refine code for VCE2.0 and related dpm code.</title>
<updated>2017-02-08T22:22:27Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-26T08:25:05Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=beeea9819d1b85ea4f4beb09d176de9889079c75'/>
<id>urn:sha1:beeea9819d1b85ea4f4beb09d176de9889079c75</id>
<content type='text'>
v2: clean up vce cg function.
    use sw cg when vce stoped.

1. implement vce_stop function.
2. not start vce when hw_init.
3. refine vce cg/pg code.
4. delete bypass mode.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rework IP block registration (v2)</title>
<updated>2016-10-25T18:38:45Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-10-13T21:41:13Z</published>
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<id>urn:sha1:a12551072126758ecb0743147054f22bf233bb7d</id>
<content type='text'>
This makes it easier to replace specific IP blocks on
asics for handling virtual_dce, DAL, etc. and for building
IP lists for hw or tables.  This also stored the status
information in the same structure.

v2: split out spelling fix into a separate patch
    add a function to add IPs to the list

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move align_mask and nop into ring funcs as well (v2)</title>
<updated>2016-10-25T18:38:38Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-10-05T14:09:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7988714237c6a548011dcd7dcce84e9f16dda427'/>
<id>urn:sha1:7988714237c6a548011dcd7dcce84e9f16dda427</id>
<content type='text'>
They are constant as well.

v2: update uvd and vce phys ring structures as well

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
