<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2018-02-28T19:18:05Z</updated>
<entry>
<title>drm/amdgpu:Fixed wrong emit frame size for enc</title>
<updated>2018-02-28T19:18:05Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-02-27T14:55:17Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=60b431b5c165514729ad0a47e18b0f99783dfc38'/>
<id>urn:sha1:60b431b5c165514729ad0a47e18b0f99783dfc38</id>
<content type='text'>
Emit frame size should match with corresponding function,
uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: separate PASID mapping from VM flush v2</title>
<updated>2018-02-19T19:20:18Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-02-04T09:32:35Z</published>
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<id>urn:sha1:c633c00bf06779ec6d5e2c01748d4753ede98f8a</id>
<content type='text'>
Stuffing the PASID mapping into the VM flush isn't flexible enough since
the PASID mapping changes not as often as we need a VM flush.

v2: add missing use of gmc_v7_0_emit_pasid_mapping

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix DW estimation on VI</title>
<updated>2018-02-19T19:19:08Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-30T15:02:38Z</published>
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<id>urn:sha1:491355937a4b0079213f37669e601eb46c08b05b</id>
<content type='text'>
Forgot to update that during recent changes.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove now superflous *_hdp operation</title>
<updated>2018-02-19T19:18:22Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-19T14:19:16Z</published>
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<id>urn:sha1:2ee150cda7bdc766cf9baca3534f3a2c0b0e8357</id>
<content type='text'>
All HDP invalidation and most flush can now be replaced by the generic
ASIC function.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement gmc_v8_0_emit_flush_gpu_tlb</title>
<updated>2018-02-19T19:18:09Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T18:14:42Z</published>
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<id>urn:sha1:5518625d6a50c1724b2b2a796fc2fb1a8f1a9c21</id>
<content type='text'>
Unify tlb flushing for gmc v8.

v2: handle UVD v6 as well

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: wire up emit_wreg for UVD v6</title>
<updated>2018-02-19T19:18:05Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T15:34:22Z</published>
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<id>urn:sha1:252998986a191e459f9ba093d48f09d90510a02f</id>
<content type='text'>
Needed for vm_flush unification.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: forward pasid to backend flush implementations</title>
<updated>2018-02-19T19:17:47Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-08T13:48:11Z</published>
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<id>urn:sha1:5a4633c4b880cf8d1fe7df9c55766205cf9bc295</id>
<content type='text'>
rd the pasid from the VM code to the emit_vm_flush function and update
all implementations with the new parameter.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Add Polaris version check</title>
<updated>2018-01-23T06:43:15Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-01-22T18:46:16Z</published>
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<id>urn:sha1:dead73d791455a0b4eb6f644ab592b7da6c670dc</id>
<content type='text'>
Add Polaris version check if firmware support UVD encode

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: rename vm_id to vmid</title>
<updated>2017-12-27T16:34:02Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-12-18T16:08:25Z</published>
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<id>urn:sha1:c4f46f22c448ff571eb8fdbe4ab71a25805228d1</id>
<content type='text'>
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm: move amd_gpu_scheduler into common location</title>
<updated>2017-12-07T16:51:56Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-12-06T16:49:39Z</published>
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<id>urn:sha1:1b1f42d8fde4fef1ed7873bf5aa91755f8c3de35</id>
<content type='text'>
This moves and renames the AMDGPU scheduler to a common location in DRM
in order to facilitate re-use by other drivers. This is mostly a straight
forward rename with no code changes.

One notable exception is the function to_drm_sched_fence(), which is no
longer a inline header function to avoid the need to export the
drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures.

Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Tested-by: Dieter Nützel &lt;Dieter@nuetzel-hh.de&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
