kernel/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c, branch linux-4.17.y

drm/amdgpu: remove now superflous *_hdp operation

2018-02-19T19:18:22Z

All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by: Christian König Acked-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: rename vm_id to vmid

2017-12-27T16:34:02Z

sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amd/amdgpu: fix UVD mc offsets

2017-12-06T17:47:22Z

When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by: Christian König Signed-off-by: Piotr Redlewski Signed-off-by: Alex Deucher

drm/amdgpu: change redundant init logs to debug level

2017-12-04T21:33:12Z

When this VF stays in exclusive mode for long, other VFs will be impacted. The redundant messages causes exclusive mode timeout when they're redirected. That is a normal use case for cloud service to redirect guest log to virtual serial port. Reviewed-by: Alex Deucher Signed-off-by: pding Signed-off-by: Alex Deucher

drm/amdgpu: various cleanups for uvd/vce.

2017-04-04T17:40:33Z

Signed-off-by: Rex Zhu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: switch ih handling to two levels (v3)

2017-03-30T03:53:37Z

Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher Signed-off-by: Ken Wang Reviewed-by: Ken Wang Signed-off-by: Alex Deucher

drm/amdgpu: change wptr to 64 bits (v2)

2017-03-30T03:53:35Z

Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by: Ken Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: read hw register to check pg status.

2017-02-13T17:43:04Z

Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: refine uvd5.0/6.0 code.

2017-02-08T22:21:52Z

1. delete redundant cg pg mask check. pg mask use to ctrl power on/down uvd. not start/stop uvd. cg mask will be check when enable mgcg. 2. no need to start uvd when initializ. when ring test/ib test/encode, uvd was enabled. when uvd idle, uvd was stopped. 3. chang cg pg sequence in powerplay. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: add get clockgating_state method for uvd v5&v6

2017-01-27T16:13:10Z

Signed-off-by: Huang Rui Reviewed-by: Christian König Signed-off-by: Alex Deucher