<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/soc15d.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2017-08-18T16:02:11Z</updated>
<entry>
<title>drm/amdgpu: fix vega10 graphic hang issue in S3 test</title>
<updated>2017-08-18T16:02:11Z</updated>
<author>
<name>Ken Wang</name>
<email>Ken.Wang@amd.com</email>
</author>
<published>2017-08-15T09:16:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d5de797ff1c91157ddefd7102aaf5f87ff222746'/>
<id>urn:sha1:d5de797ff1c91157ddefd7102aaf5f87ff222746</id>
<content type='text'>
mmVGT_INDEX_TYPE has no default value, need to make sure
it's initialized when gfx is initialized.

Signed-off-by: Ken Wang &lt;Ken.Wang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx9: move define to header file</title>
<updated>2017-05-24T21:40:29Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-05-04T14:32:33Z</published>
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<id>urn:sha1:67fb56a6dde9bddd3a57614607af255bbb732118</id>
<content type='text'>
rather than defining it locally.

Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:new PM4 entry for VI/AI</title>
<updated>2017-05-24T21:40:26Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-05-01T09:23:44Z</published>
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<id>urn:sha1:d951eeddface8bcdcb4fd95066801abface55c21</id>
<content type='text'>
TMZ package will be used for VULKAN/CHAINED-IB MCBP

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add KIQ packet defines to soc15d.h</title>
<updated>2017-05-24T21:40:14Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-04-17T19:54:55Z</published>
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<id>urn:sha1:495a746354a056ecb8c13f3baff305d0c50864ec</id>
<content type='text'>
Will be used in subsequent commits rather rather than
magic numbers.

Reviewed-by: monk liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:enable mcbp for gfx9(v2)</title>
<updated>2017-03-30T03:55:35Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-03-21T03:50:43Z</published>
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<id>urn:sha1:9ccd52eb248b0d8f0450e1201a8064f5ab1ec07e</id>
<content type='text'>
set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: init kiq and kcq for vega10</title>
<updated>2017-03-30T03:55:00Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-02-28T08:48:47Z</published>
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<id>urn:sha1:464826d67aee079e34c8b8bb652cef71c1a7dbe4</id>
<content type='text'>
Init kiq via cpu mmio and init kcq through kiq.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian KÃ¶nig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add common soc15 headers</title>
<updated>2017-03-30T03:54:31Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2017-03-06T17:41:22Z</published>
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<id>urn:sha1:8e3153ba3f623b325b00303fe6d998b868adfe0b</id>
<content type='text'>
These are used by various IP modules.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
