<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/soc15_common.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2017-12-13T22:28:07Z</updated>
<entry>
<title>drm/amdgpu: convert nbio to use callbacks (v2)</title>
<updated>2017-12-13T22:28:07Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-08T18:07:58Z</published>
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<id>urn:sha1:bf383fb64e7c8ccc96d382e38e829737389708a7</id>
<content type='text'>
Cleans up and consolidates all of the per-asic logic.

v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming)

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset</title>
<updated>2017-12-08T16:32:24Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-29T18:51:32Z</published>
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<id>urn:sha1:cd29253f650a6ab27bae8c0b8c17fb8e71f864e8</id>
<content type='text'>
Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array</title>
<updated>2017-12-08T16:18:51Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-28T22:01:21Z</published>
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<id>urn:sha1:946a4d5b301028621791e6c8b53f64c426dea1a5</id>
<content type='text'>
Handle dynamic offsets correctly in static arrays.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Use dynamic IP offset for register access on SOC15</title>
<updated>2017-12-08T16:17:56Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-27T18:20:38Z</published>
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<id>urn:sha1:b466107e8be15e1727e288639098ef6bfec1a982</id>
<content type='text'>
Update the register access macros and functions to take into
account the new dynamic IP base offsets.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro define</title>
<updated>2017-07-14T15:06:10Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-07-05T14:53:55Z</published>
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<id>urn:sha1:c708535e9ced6213b7c327eff88970e95515ec8a</id>
<content type='text'>
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Add offset variant to SOC15 macros</title>
<updated>2017-06-15T15:50:30Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2017-06-12T16:05:42Z</published>
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<id>urn:sha1:496828e78625e021ba51f4bd060c026c4cbab718</id>
<content type='text'>
Allows reading/writing via SOC15 macros with offset for
various register banks.

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Introduce new read/write macros for SOC15</title>
<updated>2017-04-28T20:37:59Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2017-04-07T11:53:31Z</published>
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<id>urn:sha1:b1bb8c0118b3b9d44a6a31ea5242bdd9ed040a9b</id>
<content type='text'>
Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add common soc15 headers</title>
<updated>2017-03-30T03:54:31Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2017-03-06T17:41:22Z</published>
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<id>urn:sha1:8e3153ba3f623b325b00303fe6d998b868adfe0b</id>
<content type='text'>
These are used by various IP modules.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
