kernel/drivers/gpu/drm/amd/amdgpu/soc15.h, branch linux-rolling-stableHosts the 0x221E linux distro kernel.https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable2025-06-24T14:03:25Zdrm/amdgpu: use common function to map ip for aqua_vanjaram2025-06-24T14:03:25ZLikun GaoLikun.Gao@amd.com2025-03-21T06:14:06Zurn:sha1:37b791d667bed3a43cbbcc5b7e7b69813e4c528f
Transfer to use function amdgpu_ip_map_init to map ip
instance for aqua_vanjaram instead of operation on
different ASIC.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add macro to calculate offset with instance2024-07-27T21:28:28ZSunil Khatrisunil.khatri@amd.com2024-07-24T17:05:56Zurn:sha1:50d10d9271f6c6542196c54275091c7b2c6edf97
Add macro definition which calculate offset of the
register with index override.
This is useful in case when there is an array of
registers which is common for all instances.
To read registers in that case it is easy to define
registers once and the index value is manually passed
to calculate proper offset of register for each instance.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add support of gfx10 register dump2024-04-26T21:22:39ZSunil Khatrisunil.khatri@amd.com2024-04-16T10:44:12Zurn:sha1:c395dbb68b294d1de9a5ac6c9faaf8ac081123c3
Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Read aquavanjaram PCIE register state2023-11-29T21:49:35ZLijo Lazarlijo.lazar@amd.com2023-10-06T08:50:45Zurn:sha1:081a6eda2b25092e1466f09eb46d829488b75730
Add support to read aqua vanjaram PCIE register state
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add soc config init for GC9.4.3 ASICs2023-06-09T13:49:39ZLijo Lazarlijo.lazar@amd.com2022-09-23T09:13:17Zurn:sha1:e56c9ef6cb35f33dc83f635419ae55adf69db9fc
Add function to initialize soc configuration information for GC 9.4.3
ASICs. Use it to map IPs and other SOC related information once IP
configuration information is available through discovery.
For GC9.4.3 compute partition related callbacks are initialized as part
of configuration init.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add helpers to access registers on different AIDs2023-06-09T13:48:05ZLe Male.ma@amd.com2022-09-27T09:51:33Zurn:sha1:2fa480d36eb302712e48dce4d2f6564b24426be3
SMN address which is larger than 32bit has different indications
through bit[34:32] on different AIDs.
v2: put smn addressing of different AIDs into asic specific place
v3: change to ext_id/ext_offset naming
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch to aqua_vanjaram_doorbell_index_init2023-06-09T13:47:35ZLe Male.ma@amd.com2022-05-24T11:44:27Zurn:sha1:1dfcdc30270a80ba5b45f922833c0c0e56d82576
New doorbell index assignment is used by aqua_vanjaram.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add IP instance map for aqua vanjaram2023-06-09T13:47:23ZLijo Lazarlijo.lazar@amd.com2022-06-29T10:15:06Zurn:sha1:cab7d478da112e66f2ad8eec7dcfc0aa2a5babe1
Add XCC logical to physical instance map for aqua vanjaram
v2:
Keep look up table only for required IPs, for others return
default mapping (Felix).
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add xcc index argument to soc15_grbm_select2023-04-18T20:28:55ZLe Male.ma@amd.com2021-11-17T08:28:51Zurn:sha1:5aa998baab3360d0f1b93d6aff3df924045f956c
To support grbm select for multiple XCD case.
v2: unify naming style
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: drop soc15_set_ip_blocks()2021-10-20T15:43:57ZAlex Deucheralexander.deucher@amd.com2021-10-11T13:44:47Zurn:sha1:7092432e3cb1a47f1ba7fe59ceb23f85bd8e09a4
No longer used since IP enumeration is now driven by
amdgpu IP discovery code.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>