<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/soc15.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2018-02-19T19:19:12Z</updated>
<entry>
<title>drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlb</title>
<updated>2018-02-19T19:19:12Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-26T14:00:43Z</published>
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<id>urn:sha1:f732b6b3c0e62bf889702d6af2b1e5436e4e9a0a</id>
<content type='text'>
Keep that at a common place instead of spread over all engines.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;felix.kuehling@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add PASID mapping for GMC v9</title>
<updated>2018-02-19T19:18:11Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-16T19:31:15Z</published>
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<id>urn:sha1:250b422833321d1d5a6e68ae8699c4e34563de0e</id>
<content type='text'>
This way we can see the PASID in VM faults.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement gmc_v9_0_emit_flush_gpu_tlb</title>
<updated>2018-02-19T19:18:09Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T20:57:53Z</published>
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<id>urn:sha1:9096d6e51a121c4cd2ea13e7b5087272425cf87a</id>
<content type='text'>
Unify tlb flushing for gmc v9.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array</title>
<updated>2017-12-08T16:18:51Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-28T22:01:21Z</published>
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<id>urn:sha1:946a4d5b301028621791e6c8b53f64c426dea1a5</id>
<content type='text'>
Handle dynamic offsets correctly in static arrays.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Dynamic initialize IP base offset</title>
<updated>2017-12-08T16:16:51Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-27T18:16:35Z</published>
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<id>urn:sha1:4522824c488e93755b10349cf6af0e967fb73186</id>
<content type='text'>
The base offsets of the IP blocks may change across
asics even though the relative register offsets
are the same for an IP.  Handle this dynamically.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: apply nbio7 for Raven (v3)</title>
<updated>2017-05-24T21:41:17Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-05-04T19:06:25Z</published>
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<id>urn:sha1:aecbe64f2b926c7422ce6f0c4d18b7f7dc4a9677</id>
<content type='text'>
nbio handles misc bus io operations. Handle
differences between different nbio bus versions.

v2: switch checks from RAVEN to APU (Alex)
    squash in raven rev id fetch
    squash in fix uninitalized hdp flush reg index for raven
v3: add some missed RAVEN to APU checks (Alex)

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add common soc15 headers</title>
<updated>2017-03-30T03:54:31Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2017-03-06T17:41:22Z</published>
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<id>urn:sha1:8e3153ba3f623b325b00303fe6d998b868adfe0b</id>
<content type='text'>
These are used by various IP modules.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
