<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/soc15.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-06-11T10:19:21Z</updated>
<entry>
<title>drm/amdgpu/soc15: skip reset on init</title>
<updated>2019-06-11T10:19:21Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-05-17T14:21:13Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f3b80306996f6f32c2b8a90f67dc207f65661281'/>
<id>urn:sha1:f3b80306996f6f32c2b8a90f67dc207f65661281</id>
<content type='text'>
commit 5887a59961e2295c5b02f39dbc0ecf9212709b7b upstream.

Not necessary on soc15 and breaks driver reload on server cards.

Acked-by: Amber Lin &lt;Amber.Lin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>Revert "drm/amdgpu: use BACO reset on vega20 if platform support"</title>
<updated>2019-02-28T03:22:30Z</updated>
<author>
<name>Candice Li</name>
<email>candice.li@amd.com</email>
</author>
<published>2019-02-25T02:59:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7db329e57b90ddebcb58fc88eedbb3082d22a957'/>
<id>urn:sha1:7db329e57b90ddebcb58fc88eedbb3082d22a957</id>
<content type='text'>
This reverts commit 2172b89e7c94605380d8c0dedf543c93f0a0b27c.

Signed-off-by: Candice Li &lt;candice.li@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge v5.0-rc7 into drm-next</title>
<updated>2019-02-18T03:27:15Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2019-02-18T03:27:15Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c06de56121e3ac0f0f1f4a081c041654ffcacd62'/>
<id>urn:sha1:c06de56121e3ac0f0f1f4a081c041654ffcacd62</id>
<content type='text'>
Backmerging for nouveau and imx that needed some fixes for next pulls.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix the incorrect external id for raven series</title>
<updated>2019-02-01T05:12:17Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2019-01-30T11:50:04Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7e4545d372b560df10fa47281ef0783a479ce435'/>
<id>urn:sha1:7e4545d372b560df10fa47281ef0783a479ce435</id>
<content type='text'>
This patch fixes the incorrect external id that kernel reports to user mode
driver. Raven2's rev_id is starts from 0x8, so its external id (0x81) should
start from rev_id + 0x79 (0x81 - 0x8). And Raven's rev_id should be 0x21 while
rev_id == 1.

Reported-by: Crystal Jin &lt;Crystal.Jin@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: check PSP support before adding the ip block</title>
<updated>2019-01-25T21:15:35Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-01-08T05:57:29Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3680b2a5b6d92747b3293ccc6783da29574147f1'/>
<id>urn:sha1:3680b2a5b6d92747b3293ccc6783da29574147f1</id>
<content type='text'>
So that we do not need to check this in every internal function.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Setting doorbell range registers earlier</title>
<updated>2019-01-25T21:15:34Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-01-14T22:32:53Z</published>
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<id>urn:sha1:7c94bc828ee7e7e64f31e40bb967b6417d7e6382</id>
<content type='text'>
HW doorbell writing routing policy: writing to doorbell
not in SDMA/IH/MM/ACV doorbell range will be routed to CP.
So CP doorbell routing depends on doorbell range setting
of above blocks. Setting doorbell range of above blocks
earlier (soc15_common_hw_init) to make sure CP doorbell
writing be routed to CP block.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/soc15: return proper error codes in baco reset</title>
<updated>2019-01-25T21:15:34Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-01-14T19:56:42Z</published>
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<id>urn:sha1:1f46df61a148da7263165079b4874d61525c8ae1</id>
<content type='text'>
Rather than just -1.

Reviewed-by: JimQu &lt;Jim.Qu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use BACO reset on vega20 if platform support</title>
<updated>2019-01-25T21:15:34Z</updated>
<author>
<name>Jim Qu</name>
<email>Jim.Qu@amd.com</email>
</author>
<published>2018-11-08T06:07:22Z</published>
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<id>urn:sha1:2172b89e7c94605380d8c0dedf543c93f0a0b27c</id>
<content type='text'>
Signed-off-by: Jim Qu &lt;Jim.Qu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use BACO reset if platform support (v2)</title>
<updated>2019-01-25T21:15:33Z</updated>
<author>
<name>Jim Qu</name>
<email>Jim.Qu@amd.com</email>
</author>
<published>2018-11-07T04:29:39Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e2b6d053b1077d6eef025e7869690c630ab29d0c'/>
<id>urn:sha1:e2b6d053b1077d6eef025e7869690c630ab29d0c</id>
<content type='text'>
It will fall back to use mode1 reset if platform does not support BACO
feature.

v2: squash in warning fix (Alex)

Signed-off-by: Jim Qu &lt;Jim.Qu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/soc15: add need_reset_on_init asic callback for SOC15 (v2)</title>
<updated>2019-01-14T20:04:56Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-11-01T05:00:57Z</published>
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<id>urn:sha1:9281f12cabb09059ae60603e14cc9cd98b02febb</id>
<content type='text'>
SOC15 chips require a reset if the driver was previously loaded
because the PSP can only be loaded once between each reset.

v2: rebase, handle multiple asic funcs

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
