<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/soc15.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-03-21T19:36:53Z</updated>
<entry>
<title>drm/amdgpu/soc15: initialize reg base for vega12</title>
<updated>2018-03-21T19:36:53Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2018-03-12T10:25:15Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3084eb0011b38cceaafb9312ad90fe20d343daa7'/>
<id>urn:sha1:3084eb0011b38cceaafb9312ad90fe20d343daa7</id>
<content type='text'>
Initialize the IP offsets for vega12.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/soc15: Add external_rev_id for vega12.</title>
<updated>2018-03-21T19:36:52Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-12-14T11:02:47Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f559fe2bc1c1c338e5e9f4fa04e2ab12e59d1818'/>
<id>urn:sha1:f559fe2bc1c1c338e5e9f4fa04e2ab12e59d1818</id>
<content type='text'>
Add external_rev_id for vega12.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/soc15: update vega12 cg_flags</title>
<updated>2018-03-21T19:36:52Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2017-12-25T05:16:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e4a387558ea869c8623e2e81e2844ef472c55410'/>
<id>urn:sha1:e4a387558ea869c8623e2e81e2844ef472c55410</id>
<content type='text'>
Add the appropriate clockgating flags for vega12

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/soc15: add support for vega12</title>
<updated>2018-03-21T19:36:51Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-07T03:35:19Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=692069a1a4f137bb45a3d43af576de8d1ff89c7d'/>
<id>urn:sha1:692069a1a4f137bb45a3d43af576de8d1ff89c7d</id>
<content type='text'>
Add the IP blocks, clock and powergating flags, and
common clockgating support.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Delete dead code when early init</title>
<updated>2018-03-19T18:34:46Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-03-16T04:40:16Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=699f47951e79b6e0ad33f7d7406c6a574293e339'/>
<id>urn:sha1:699f47951e79b6e0ad33f7d7406c6a574293e339</id>
<content type='text'>
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Remove wrapper layer of smu ip functions</title>
<updated>2018-03-15T14:57:50Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-03-12T11:52:23Z</published>
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<id>urn:sha1:b905090d2bae2e6189511714a7b88691b439c5a1</id>
<content type='text'>
1. delete amdgpu_powerplay.c used for wrapping smu ip functions
2. delete struct pp_instance,
3. make struct hwmgr as the smu hw handle.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move getting pcie info to common code</title>
<updated>2018-03-14T21:01:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-09T20:14:11Z</published>
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<id>urn:sha1:5494d8640ffc1df6096fd37943948ab46a152850</id>
<content type='text'>
No need to replicate it in several places.

Reviewed-by: Rex Zhu &lt;rezhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/soc15: always load the psp module</title>
<updated>2018-03-14T21:01:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-09T20:22:28Z</published>
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<id>urn:sha1:3cdfe700567a653ba18dfe012f74b6b75b4bd946</id>
<content type='text'>
Regardless of whether the user has selected psp fw loading or
not.  It's still needed for GPU reset among other things.
There are already guards in place to avoid setting up the full
psp if PSP fw loading is not enabled.

Reviewed-by: Rex Zhu &lt;rezhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use adev-&gt;firmware to determine whether to load the PSP module</title>
<updated>2018-03-14T21:01:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-09T20:19:44Z</published>
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<id>urn:sha1:454bbbf915cd089d326cf39a1929bb8cee47d1d4</id>
<content type='text'>
The per device firmware load method is limited to what makes sense for
that asic rather than whatever arbitrary value may have been set by the
user.

Reviewed-by: Rex Zhu &lt;rezhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move firmware loading type setup to common code</title>
<updated>2018-03-14T21:01:15Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-09T20:06:35Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=19aede779138c0514b8e96c24473f22aaf21be65'/>
<id>urn:sha1:19aede779138c0514b8e96c24473f22aaf21be65</id>
<content type='text'>
No need to replicate it in several places.

Reviewed-by: Rex Zhu &lt;rezhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
