<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/soc15.c, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-01-19T22:32:07Z</updated>
<entry>
<title>drm/amdgpu: disable MMHUB power gating on raven</title>
<updated>2018-01-19T22:32:07Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2017-12-14T05:47:16Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=400b6afbaa949914460e5fd1d769c5e26ef1f6b8'/>
<id>urn:sha1:400b6afbaa949914460e5fd1d769c5e26ef1f6b8</id>
<content type='text'>
MMHUB power gating still has issue, and doesn't work on raven at current. So
disable it for the moment.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: rename amdgpu_get_pcie_info</title>
<updated>2017-12-18T16:00:08Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-15T21:49:33Z</published>
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<id>urn:sha1:041d9d93b5dba8fa41134a4e5fc7a432b76fa308</id>
<content type='text'>
add device to the name for consistency.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename ip block helper functions</title>
<updated>2017-12-18T15:59:40Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-15T21:18:00Z</published>
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<id>urn:sha1:2990a1fc012e1bb4523a54d2c27eebc21a2c7e7e</id>
<content type='text'>
add device to the name for consistency.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: drop soc15_init_golden_registers</title>
<updated>2017-12-13T22:28:08Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-08T18:18:23Z</published>
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<id>urn:sha1:2dd744e0ce2a34cb6b77a80385eee827a6a1ee24</id>
<content type='text'>
The golden register arrays were empty so the function was
effectively useless.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: convert nbio to use callbacks (v2)</title>
<updated>2017-12-13T22:28:07Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-08T18:07:58Z</published>
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<id>urn:sha1:bf383fb64e7c8ccc96d382e38e829737389708a7</id>
<content type='text'>
Cleans up and consolidates all of the per-asic logic.

v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming)

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/admgpu: Reduce the usage of soc15ip.h</title>
<updated>2017-12-08T16:35:19Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-29T19:04:58Z</published>
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<id>urn:sha1:4fd09a19a6337b1a58d6de8777e2210cec55ae84</id>
<content type='text'>
Remove the header where it's not used.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset</title>
<updated>2017-12-08T16:32:24Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-29T18:51:32Z</published>
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<id>urn:sha1:cd29253f650a6ab27bae8c0b8c17fb8e71f864e8</id>
<content type='text'>
Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array</title>
<updated>2017-12-08T16:18:51Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-28T22:01:21Z</published>
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<id>urn:sha1:946a4d5b301028621791e6c8b53f64c426dea1a5</id>
<content type='text'>
Handle dynamic offsets correctly in static arrays.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Dynamic initialize IP base offset</title>
<updated>2017-12-08T16:16:51Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-27T18:16:35Z</published>
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<id>urn:sha1:4522824c488e93755b10349cf6af0e967fb73186</id>
<content type='text'>
The base offsets of the IP blocks may change across
asics even though the relative register offsets
are the same for an IP.  Handle this dynamically.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include:cleanup vega10 header files.</title>
<updated>2017-12-06T17:48:22Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-24T04:31:36Z</published>
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<id>urn:sha1:fb960bd28354805a7e2a6dbdf8d8d07a5160d0cd</id>
<content type='text'>
Remove asic_reg/vega10 folder.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
