kernel/drivers/gpu/drm/amd/amdgpu/si_dma.c, branch linux-4.16.y

drm/amdgpu: rename vm_id to vmid

2017-12-27T16:34:02Z

sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: rename amdgpu_wb_* functions

2017-12-18T15:59:07Z

add device for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: change redundant init logs to debug level

2017-12-04T21:33:12Z

When this VF stays in exclusive mode for long, other VFs will be impacted. The redundant messages causes exclusive mode timeout when they're redirected. That is a normal use case for cloud service to redirect guest log to virtual serial port. Reviewed-by: Alex Deucher Signed-off-by: pding Signed-off-by: Alex Deucher

drm/amdgpu: Add copy_pte_num_dw member in amdgpu_vm_pte_funcs

2017-09-26T19:14:22Z

Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping(). Signed-off-by: Yong Zhao Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Fix a bug in amdgpu_fill_buffer()

2017-09-26T19:14:21Z

When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by: Yong Zhao Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v3)

2017-03-30T03:55:50Z

v2: fix for all sdma engines v3: squash in fix for SI/CI Signed-off-by: Junwei Zhang Reviewed-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: expand pte flags to uint64_t

2017-03-30T03:53:38Z

Necessary for new asics. Signed-off-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: switch ih handling to two levels (v3)

2017-03-30T03:53:37Z

Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher Signed-off-by: Ken Wang Reviewed-by: Ken Wang Signed-off-by: Alex Deucher

drm/amdgpu: change wptr to 64 bits (v2)

2017-03-30T03:53:35Z

Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by: Ken Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: move misc si headers into amdgpu

2017-01-27T17:20:41Z

Move these to the amdgpu directory to match what we do for other asics. Acked-by: Christian König Signed-off-by: Alex Deucher