<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2018-04-03T17:52:58Z</updated>
<entry>
<title>drm/amdgpu/sdma: fix mask in emit_pipeline_sync</title>
<updated>2018-04-03T17:52:58Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-27T20:53:52Z</published>
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<id>urn:sha1:4a8e06f7aad797e92413a3042d09d3b385fa1fda</id>
<content type='text'>
Needs to be a 32 bit mask.

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Clean sdma wptr register when only enable wptr polling</title>
<updated>2018-03-07T21:10:35Z</updated>
<author>
<name>Emily Deng</name>
<email>Emily.Deng@amd.com</email>
</author>
<published>2018-03-07T01:47:43Z</published>
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<id>urn:sha1:4062119b9d958df33bcda703dc3ac646908fa861</id>
<content type='text'>
The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

v2:add comment above the code and correct coding style

Reviewed-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: change amdgpu_ttm_set_active_vram_size</title>
<updated>2018-03-05T20:37:12Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-03-01T10:01:52Z</published>
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<id>urn:sha1:57adc4cef617d7284ac7676e14533268e73e3699</id>
<content type='text'>
Instead of setting the active VRAM size directly provide a the info if
we can use the buffer functions or not.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: separate PASID mapping from VM flush v2</title>
<updated>2018-02-19T19:20:18Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-02-04T09:32:35Z</published>
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<id>urn:sha1:c633c00bf06779ec6d5e2c01748d4753ede98f8a</id>
<content type='text'>
Stuffing the PASID mapping into the VM flush isn't flexible enough since
the PASID mapping changes not as often as we need a VM flush.

v2: add missing use of gmc_v7_0_emit_pasid_mapping

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix DW estimation on VI</title>
<updated>2018-02-19T19:19:08Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-30T15:02:38Z</published>
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<id>urn:sha1:491355937a4b0079213f37669e601eb46c08b05b</id>
<content type='text'>
Forgot to update that during recent changes.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: revert "Add support for filling a buffer with 64 bit value"</title>
<updated>2018-02-19T19:18:55Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-24T18:58:45Z</published>
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<id>urn:sha1:44e1baeb6321fb4ce1dbc50c4cb895b671b2fbf9</id>
<content type='text'>
This reverts commit 7bdc53f925af085ffa0580f10489f82b36cc2f1c and commit
330df03b3abf944f8f5180f2abc61367749984c0.

Neither are needed any more.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove now superflous *_hdp operation</title>
<updated>2018-02-19T19:18:22Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-19T14:19:16Z</published>
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<id>urn:sha1:2ee150cda7bdc766cf9baca3534f3a2c0b0e8357</id>
<content type='text'>
All HDP invalidation and most flush can now be replaced by the generic
ASIC function.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement gmc_v8_0_emit_flush_gpu_tlb</title>
<updated>2018-02-19T19:18:09Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T18:14:42Z</published>
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<id>urn:sha1:5518625d6a50c1724b2b2a796fc2fb1a8f1a9c21</id>
<content type='text'>
Unify tlb flushing for gmc v8.

v2: handle UVD v6 as well

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: wire up emit_wreg for SDMA v3</title>
<updated>2018-02-19T19:18:04Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T15:33:49Z</published>
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<id>urn:sha1:3d31d4cb2cc4aba99d485ee052dffdf934a1bfca</id>
<content type='text'>
Needed for vm_flush unification.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: forward pasid to backend flush implementations</title>
<updated>2018-02-19T19:17:47Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-08T13:48:11Z</published>
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<id>urn:sha1:5a4633c4b880cf8d1fe7df9c55766205cf9bc295</id>
<content type='text'>
rd the pasid from the VM code to the emit_vm_flush function and update
all implementations with the new parameter.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
