<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-03-21T19:36:47Z</updated>
<entry>
<title>drm/amdgpu/mmhub: add clockgating support for vega12</title>
<updated>2018-03-21T19:36:47Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-09-01T20:39:10Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f8d27677e1015b47367c9f16155b770c34d2bcf4'/>
<id>urn:sha1:f8d27677e1015b47367c9f16155b770c34d2bcf4</id>
<content type='text'>
Treat it the same as vega10 for now.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use the TTM dummy page instead of allocating one</title>
<updated>2018-02-27T04:09:36Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-02-22T07:35:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=92e71b0676447fff40c1e747b2585a9d11c5fca2'/>
<id>urn:sha1:92e71b0676447fff40c1e747b2585a9d11c5fca2</id>
<content type='text'>
We have a global dummy page in TTM, use that one instead of allocating a
new one.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add mmhub powergating set by smu</title>
<updated>2018-02-19T19:19:41Z</updated>
<author>
<name>Eric Huang</name>
<email>JinHuiEric.Huang@amd.com</email>
</author>
<published>2018-02-06T21:21:05Z</published>
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<id>urn:sha1:7e452ce9c96e829a936a2901915eeef3ec6e85fe</id>
<content type='text'>
PSP will disable legacy mmhub PG setting that is programming
registers, and drive will use SMC message to
set it up.

Signed-off-by: Eric Huang &lt;JinHuiEric.Huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.h</title>
<updated>2018-02-19T19:17:43Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T13:52:22Z</published>
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<id>urn:sha1:770d13b19fdf365a99e559f1d47f1380910a947d</id>
<content type='text'>
And rename it to amdgpu_gmc as well.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Samuel Li &lt;Samuel.Li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Update MMHUB power gating register settings</title>
<updated>2018-02-19T19:17:38Z</updated>
<author>
<name>Yong Zhao</name>
<email>yong.zhao@amd.com</email>
</author>
<published>2017-12-21T21:19:03Z</published>
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<id>urn:sha1:c8553f4bd29d681706dd97519e2daddf90505978</id>
<content type='text'>
The new register settings are needed to fix a tlb invalidation issue
when MMHUB power gating is turned on for Raven.

Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Eric Huang &lt;JinhuiEric.Huang@amd.com&gt;
Reviewed-by: Eric Huang &lt;JinhuiEric.Huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement 2+1 PD support for Raven v3</title>
<updated>2017-12-18T16:53:08Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-12-05T14:23:26Z</published>
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<id>urn:sha1:6a42fd6fbf5340968b1fb41bf6a700699ddb5a13</id>
<content type='text'>
Instead of falling back to 2 level and very limited address space use
2+1 PD support and 128TB + 512GB of virtual address space.

v2: cleanup defines, rebase on top of level enum
v3: fix inverted check in hardware setup

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-and-Tested-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/admgpu: Reduce the usage of soc15ip.h</title>
<updated>2017-12-08T16:35:19Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-29T19:04:58Z</published>
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<id>urn:sha1:4fd09a19a6337b1a58d6de8777e2210cec55ae84</id>
<content type='text'>
Remove the header where it's not used.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include:cleanup vega10 header files.</title>
<updated>2017-12-06T17:48:22Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-24T04:31:36Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=fb960bd28354805a7e2a6dbdf8d8d07a5160d0cd'/>
<id>urn:sha1:fb960bd28354805a7e2a6dbdf8d8d07a5160d0cd</id>
<content type='text'>
Remove asic_reg/vega10 folder.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include:cleanup vega10 mmhub header files.</title>
<updated>2017-12-06T17:48:20Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-23T06:30:43Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=65417d9f553b5877a3fa4e32544e6a2bcb539ea9'/>
<id>urn:sha1:65417d9f553b5877a3fa4e32544e6a2bcb539ea9</id>
<content type='text'>
Cleanup asic_reg/vega10/MMHUB folder.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include:cleanup vega10 athub header files.</title>
<updated>2017-12-06T17:48:17Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-16T09:50:10Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6ce682251dd7dc4dab6813b032622f8381208e42'/>
<id>urn:sha1:6ce682251dd7dc4dab6813b032622f8381208e42</id>
<content type='text'>
Cleanup asic_reg/vega10/ATHUB folder,remove unused files.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
