<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-03-21T19:36:46Z</updated>
<entry>
<title>drm/amdgpu/gmc9: add vega12 support (v2)</title>
<updated>2018-03-21T19:36:46Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-14T01:25:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=273a14cd1514345d66911de01d3bbe3c4c107e5c'/>
<id>urn:sha1:273a14cd1514345d66911de01d3bbe3c4c107e5c</id>
<content type='text'>
Same as vega10.

v2: squash in golden regs fix from Feifei

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move IH clientid defs to separate file</title>
<updated>2018-03-14T20:16:35Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2018-03-08T21:44:47Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3760f76cbebb455deaaa3e64ad5feb25222e65a9'/>
<id>urn:sha1:3760f76cbebb455deaaa3e64ad5feb25222e65a9</id>
<content type='text'>
This is preparation for sharing client ID definitions
between amdgpu and amdkfd

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: query vram type from atombios</title>
<updated>2018-03-14T19:38:26Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2018-03-08T10:01:24Z</published>
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<id>urn:sha1:1e09b05386f32efbebb798cf0341eca4b424c960</id>
<content type='text'>
The vram type for dGPU is stored in umc_info while sys mem type
for APU is stored in integratedsysteminfo

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increase gart size to 512MB</title>
<updated>2018-02-28T19:18:05Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2018-01-23T11:17:56Z</published>
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<id>urn:sha1:fe19b862f18ec09c34dc09e8134e08dbfd601876</id>
<content type='text'>
256MB is too small consider PTE/PDE shadow and TTM
eviction activity

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: skip ECC for SRIOV in gmc late_init</title>
<updated>2018-02-28T19:18:03Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2018-01-18T08:58:04Z</published>
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<id>urn:sha1:7b6cbae2b15b13378995aa8ec049083713d4fbcc</id>
<content type='text'>
Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Correct VRAM width for APUs with GMC9</title>
<updated>2018-02-27T04:09:47Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2018-02-26T14:09:26Z</published>
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<id>urn:sha1:585b7f161c85bd5ca675b97580faf21c506541e3</id>
<content type='text'>
DDR4 has a 64-bit width not 128-bits.  It was reporting
twice the width.  Tested with my Ryzen 2400G.

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: separate PASID mapping from VM flush v2</title>
<updated>2018-02-19T19:20:18Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-02-04T09:32:35Z</published>
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<id>urn:sha1:c633c00bf06779ec6d5e2c01748d4753ede98f8a</id>
<content type='text'>
Stuffing the PASID mapping into the VM flush isn't flexible enough since
the PASID mapping changes not as often as we need a VM flush.

v2: add missing use of gmc_v7_0_emit_pasid_mapping

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Avoid get vram info from atom bios on emulation mode</title>
<updated>2018-02-19T19:19:48Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2018-02-06T22:29:35Z</published>
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<id>urn:sha1:3d918c0ed26091beb767a8d23c4226706b0e8e88</id>
<content type='text'>
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlb</title>
<updated>2018-02-19T19:19:12Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-26T14:00:43Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f732b6b3c0e62bf889702d6af2b1e5436e4e9a0a'/>
<id>urn:sha1:f732b6b3c0e62bf889702d6af2b1e5436e4e9a0a</id>
<content type='text'>
Keep that at a common place instead of spread over all engines.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;felix.kuehling@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add optional ring to *_hdp callbacks</title>
<updated>2018-02-19T19:18:20Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-19T13:17:40Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=698825653fdf1a696e1b9458ed9fc4aa2c6587d4'/>
<id>urn:sha1:698825653fdf1a696e1b9458ed9fc4aa2c6587d4</id>
<content type='text'>
This adds an optional ring to the invalidate_hdp and flush_hdp
callbacks. If the ring isn't specified or the emit_wreg function not
available the HDP operation will be done with the CPU otherwise by
writing on the ring.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
