<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2018-02-27T04:09:36Z</updated>
<entry>
<title>drm/amdgpu: use the TTM dummy page instead of allocating one</title>
<updated>2018-02-27T04:09:36Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-02-22T07:35:11Z</published>
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<id>urn:sha1:92e71b0676447fff40c1e747b2585a9d11c5fca2</id>
<content type='text'>
We have a global dummy page in TTM, use that one instead of allocating a
new one.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.h</title>
<updated>2018-02-19T19:17:43Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T13:52:22Z</published>
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<id>urn:sha1:770d13b19fdf365a99e559f1d47f1380910a947d</id>
<content type='text'>
And rename it to amdgpu_gmc as well.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Samuel Li &lt;Samuel.Li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement 2+1 PD support for Raven v3</title>
<updated>2017-12-18T16:53:08Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-12-05T14:23:26Z</published>
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<id>urn:sha1:6a42fd6fbf5340968b1fb41bf6a700699ddb5a13</id>
<content type='text'>
Instead of falling back to 2 level and very limited address space use
2+1 PD support and 128TB + 512GB of virtual address space.

v2: cleanup defines, rebase on top of level enum
v3: fix inverted check in hardware setup

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-and-Tested-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/admgpu: Reduce the usage of soc15ip.h</title>
<updated>2017-12-08T16:35:19Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>Shaoyun.Liu@amd.com</email>
</author>
<published>2017-11-29T19:04:58Z</published>
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<id>urn:sha1:4fd09a19a6337b1a58d6de8777e2210cec55ae84</id>
<content type='text'>
Remove the header where it's not used.

Acked-by: Christian Konig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Shaoyun Liu &lt;Shaoyun.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include:cleanup vega10 header files.</title>
<updated>2017-12-06T17:48:22Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-24T04:31:36Z</published>
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<id>urn:sha1:fb960bd28354805a7e2a6dbdf8d8d07a5160d0cd</id>
<content type='text'>
Remove asic_reg/vega10 folder.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include:cleanup vega10 gc header files.</title>
<updated>2017-12-06T17:48:20Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-24T02:29:00Z</published>
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<id>urn:sha1:cde5c34f63a6bbd082e3ce993919f23f1ac5fb68</id>
<content type='text'>
Cleanup asic_reg/vega10/GC folder.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:halt when vm fault</title>
<updated>2017-09-26T19:14:22Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-07-04T08:40:58Z</published>
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<id>urn:sha1:4bd9a67e17b9a2c1b0ca55e7dfc5a711c161373d</id>
<content type='text'>
only with this way we can debug the VMC page fault issue

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: fix BANK_SELECT on Vega10 (v2)</title>
<updated>2017-08-29T19:27:48Z</updated>
<author>
<name>Roger He</name>
<email>Hongbo.He@amd.com</email>
</author>
<published>2017-08-24T06:57:57Z</published>
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<id>urn:sha1:a3ce364558faa12c4f25466dfc89eb3146b8063c</id>
<content type='text'>
BANK_SELECT should always be FRAGMENT_SIZE + 3 due to 8-entry (2^3)
per cache line in L2 TLB for Vega10.

v2: agd: fix warning

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Roger He &lt;Hongbo.He@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: store fragment_size in vm_manager</title>
<updated>2017-08-17T19:46:08Z</updated>
<author>
<name>Roger He</name>
<email>Hongbo.He@amd.com</email>
</author>
<published>2017-08-11T12:00:41Z</published>
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<id>urn:sha1:e618d306ded38dc9d37c04dc37e24bf9d62e9c7b</id>
<content type='text'>
adds fragment_size in the vm_manager structure and
implements hardware setup for it.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Roger He &lt;Hongbo.He@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix Vega10 HW config for 2MB pages</title>
<updated>2017-08-17T19:45:58Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-07-29T11:28:55Z</published>
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<id>urn:sha1:dbcca4aab1b2e1983e5432cb2a1d4f5f1d8b4750</id>
<content type='text'>
Those values weren't correct. This should result in quite some speedup.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
