kernel/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c, branch linux-4.17.y

drm/amdgpu: set COMPUTE_PGM_RSRC1 for SGPR/VGPR clearing shaders

2018-04-25T03:19:57Z

Otherwise, the SQ may skip some of the register writes, or shader waves may be allocated where we don't expect them, so that as a result we don't actually reset all of the register SRAMs. This can lead to spurious ECC errors later on if a shader uses an uninitialized register. Signed-off-by: Nicolai Hähnle Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amdgpu: Add support for SRBM selection v3

2018-04-03T18:08:44Z

Also remove code duplication in write and read regs functions. This also fixes potential missing unlock in amdgpu_debugfs_regs_write in case get_user would fail. v2: Add SRBM mutex locking. v3: Fix TO counter and fix comment location. Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: separate PASID mapping from VM flush v2

2018-02-19T19:20:18Z

Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

Revert "drm/amdgpu/gfx8: Fix compute ring failure after resetting"

2018-02-19T19:19:12Z

This reverts commit 75737cb4eb78c7f185e4700b4aa20cf7a3381aca. Fixes compute rings test failure on bare metal during full GPU reset. RCA: the ring buffer has to be filled with valid packets (such as NOPs) first before submitting MAP_QUEUEs packet into KIQ. Once a compute engine is mapped, it will immediately execute the ring buffer if the RTPR is not equal to the WTPR from the MQD. It could lead to engine hang if the ring buffer filled with random data. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: move static CSA address to top of address space v2

2018-02-19T19:18:48Z

Move the CSA area to the top of the VA space to avoid clashing with HMM/ATC in the lower range on GFX9. v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA hole on GFX9 as well. Signed-off-by: Christian König Acked-by: Alex Deucher Acked-by: Monk Liu Signed-off-by: Alex Deucher

drm/amdgpu: consistently use AMDGPU_CSA_VADDR

2018-02-19T19:18:30Z

Instead of repeating this multiple times. Signed-off-by: Christian König Reviewed-by: Alex Deucher Acked-by: Monk Liu Signed-off-by: Alex Deucher

drm/amdgpu: remove now superflous *_hdp operation

2018-02-19T19:18:22Z

All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by: Christian König Acked-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: implement gmc_v8_0_emit_flush_gpu_tlb

2018-02-19T19:18:09Z

Unify tlb flushing for gmc v8. v2: handle UVD v6 as well Signed-off-by: Christian König Acked-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: wire up emit_wreg for gfx v8

2018-02-19T19:18:01Z

Needed for vm_flush unification. v2: handle compute rings as well Signed-off-by: Christian König Acked-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: forward pasid to backend flush implementations

2018-02-19T19:17:47Z

rd the pasid from the VM code to the emit_vm_flush function and update all implementations with the new parameter. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher