<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
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<updated>2019-01-10T17:01:06Z</updated>
<entry>
<title>drm/edid: Pass connector to AVI infoframe functions</title>
<updated>2019-01-10T17:01:06Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2019-01-08T17:28:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=13d0add333afea7b2fef77473232b10dea3627dd'/>
<id>urn:sha1:13d0add333afea7b2fef77473232b10dea3627dd</id>
<content type='text'>
Make life easier for drivers by simply passing the connector
to drm_hdmi_avi_infoframe_from_display_mode() and
drm_hdmi_avi_infoframe_quant_range(). That way drivers don't
need to worry about is_hdmi2_sink mess.

v2: Make is_hdmi2_sink() return true for sil-sii8620
    Adapt to omap/vc4 changes

Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: "Christian König" &lt;christian.koenig@amd.com&gt;
Cc: "David (ChunMing) Zhou" &lt;David1.Zhou@amd.com&gt;
Cc: Archit Taneja &lt;architt@codeaurora.org&gt;
Cc: Andrzej Hajda &lt;a.hajda@samsung.com&gt;
Cc: Laurent Pinchart &lt;Laurent.pinchart@ideasonboard.com&gt;
Cc: Inki Dae &lt;inki.dae@samsung.com&gt;
Cc: Joonyoung Shim &lt;jy0922.shim@samsung.com&gt;
Cc: Seung-Woo Kim &lt;sw0312.kim@samsung.com&gt;
Cc: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Cc: Russell King &lt;linux@armlinux.org.uk&gt;
Cc: CK Hu &lt;ck.hu@mediatek.com&gt;
Cc: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Cc: Rob Clark &lt;robdclark@gmail.com&gt;
Cc: Ben Skeggs &lt;bskeggs@redhat.com&gt;
Cc: Tomi Valkeinen &lt;tomi.valkeinen@ti.com&gt;
Cc: Sandy Huang &lt;hjc@rock-chips.com&gt;
Cc: "Heiko Stübner" &lt;heiko@sntech.de&gt;
Cc: Benjamin Gaignard &lt;benjamin.gaignard@linaro.org&gt;
Cc: Vincent Abriou &lt;vincent.abriou@st.com&gt;
Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Cc: Eric Anholt &lt;eric@anholt.net&gt;
Cc: Shawn Guo &lt;shawnguo@kernel.org&gt;
Cc: Ilia Mirkin &lt;imirkin@alum.mit.edu&gt;
Cc: amd-gfx@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
Cc: nouveau@lists.freedesktop.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Russell King &lt;rmk+kernel@armlinux.org.uk&gt;
Reviewed-by: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Reviewed-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190108172828.15184-1-ville.syrjala@linux.intel.com
</content>
</entry>
<entry>
<title>drm/amdgpu: move more defines into amdgpu_irq.h</title>
<updated>2018-09-27T02:09:22Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-09-17T13:29:28Z</published>
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<id>urn:sha1:1ffdeca64856e0149e7fb341617f47cb038df543</id>
<content type='text'>
Everything that isn't related to the IH ring.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: make function pointers mandatory</title>
<updated>2018-09-27T02:09:21Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-09-17T13:41:45Z</published>
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<id>urn:sha1:f54b30d70bc606f7a154edba5883c7fa23838e9f</id>
<content type='text'>
We always want those to be setup correctly.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable ABGR and XBGR formats (v2)</title>
<updated>2018-08-27T16:10:19Z</updated>
<author>
<name>Mauro Rossi</name>
<email>issor.oruam@gmail.com</email>
</author>
<published>2018-08-12T19:43:02Z</published>
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<id>urn:sha1:00ecc6e6d4eeba9681ec91f9601a9ed1a68a9e7f</id>
<content type='text'>
Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled

(v2) Crossbar registers are defined and used to swap red and blue channels,
     keeping the existing coding style in each of the dce modules.
     After setting crossbar bits in fb_swap, use bitwise OR for big endian
     where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()

Signed-off-by: Mauro Rossi &lt;issor.oruam@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move display definitions into amdgpu_display header</title>
<updated>2018-08-27T16:10:04Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2018-08-09T14:50:12Z</published>
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<id>urn:sha1:5df585258f9ff5d5b653f6a162dc389c597c5714</id>
<content type='text'>
Demangle amdgpu.h.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Use newly added interrupt source defs for VI v3.</title>
<updated>2018-07-13T19:45:30Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2018-05-25T14:06:52Z</published>
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<id>urn:sha1:091aec0b4e26c8d31b6c211b57a2ea2c5b985ca9</id>
<content type='text'>
v2: Rebase
v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: separate gpu address from bo pin</title>
<updated>2018-07-10T19:15:39Z</updated>
<author>
<name>Junwei Zhang</name>
<email>Jerry.Zhang@amd.com</email>
</author>
<published>2018-06-25T04:51:14Z</published>
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<id>urn:sha1:7b7c6c81b3a370b46b0c48f4ab7ac3be83237a12</id>
<content type='text'>
It could be got by amdgpu_bo_gpu_offset() if need

Signed-off-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add VEGAM support to the legacy DCE 11 module</title>
<updated>2018-05-15T18:44:02Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-04-19T21:38:46Z</published>
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<id>urn:sha1:221adb2172f10ebc3a1f86c18923692a58cff1de</id>
<content type='text'>
DC is preferred.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move GEM BO to drm_framebuffer</title>
<updated>2018-04-11T18:07:56Z</updated>
<author>
<name>Daniel Stone</name>
<email>daniels@collabora.com</email>
</author>
<published>2018-03-30T14:11:38Z</published>
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<id>urn:sha1:e68d14dd4ebaf596bf0c237ba82f815c2f561dec</id>
<content type='text'>
Since drm_framebuffer can now store GEM objects directly, place them
there rather than in our own subclass. As this makes the framebuffer
create_handle and destroy functions the same as the GEM framebuffer
helper, we can reuse those.

Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Daniel Stone &lt;daniels@collabora.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Christian König &lt;christian.koenig@amd.com&gt;
Cc: David (ChunMing) Zhou &lt;David1.Zhou@amd.com&gt;
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: save/restore backlight level in legacy dce code</title>
<updated>2018-03-14T20:08:40Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-08T14:56:01Z</published>
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<id>urn:sha1:a59b3c80fd0041223ccf720504974a543b81b1d0</id>
<content type='text'>
Save/restore the backlight level scratch register in S3/S4 so the
backlight level comes back at the previously requested level.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=199047
Fixes: 4ec6ecf48c64d (drm/amdgpu: drop scratch regs save and restore from S3/S4 handling)
Acked-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
