<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/cik_sdma.c, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
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<updated>2018-04-24T07:43:05Z</updated>
<entry>
<title>drm/amdgpu/sdma: fix mask in emit_pipeline_sync</title>
<updated>2018-04-24T07:43:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-03-27T20:53:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=49d52e9ef94092d15107e0dfa5c38e9ebf1c312c'/>
<id>urn:sha1:49d52e9ef94092d15107e0dfa5c38e9ebf1c312c</id>
<content type='text'>
commit 4a8e06f7aad797e92413a3042d09d3b385fa1fda upstream.

Needs to be a 32 bit mask.

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>drm/amdgpu: rename vm_id to vmid</title>
<updated>2017-12-27T16:34:02Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-12-18T16:08:25Z</published>
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<id>urn:sha1:c4f46f22c448ff571eb8fdbe4ab71a25805228d1</id>
<content type='text'>
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename amdgpu_wb_* functions</title>
<updated>2017-12-18T15:59:07Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-14T21:03:43Z</published>
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<id>urn:sha1:131b4b3686b701079e8fb82eb9384c8acdd3fc72</id>
<content type='text'>
add device for consistency.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: change redundant init logs to debug level</title>
<updated>2017-12-04T21:33:12Z</updated>
<author>
<name>pding</name>
<email>Pixel.Ding@amd.com</email>
</author>
<published>2017-10-26T01:30:38Z</published>
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<id>urn:sha1:9953b72f9c9cb7733334753788faab33ccc4dc0a</id>
<content type='text'>
When this VF stays in exclusive mode for long, other VFs will be
impacted.

The redundant messages causes exclusive mode timeout when they're
redirected. That is a normal use case for cloud service to redirect
guest log to virtual serial port.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: pding &lt;Pixel.Ding@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add copy_pte_num_dw member in amdgpu_vm_pte_funcs</title>
<updated>2017-09-26T19:14:22Z</updated>
<author>
<name>Yong Zhao</name>
<email>yong.zhao@amd.com</email>
</author>
<published>2017-09-19T16:58:15Z</published>
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<id>urn:sha1:e6d921974a51e607515b39baa8d1c3f1a27d008b</id>
<content type='text'>
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping().

Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix a bug in amdgpu_fill_buffer()</title>
<updated>2017-09-26T19:14:21Z</updated>
<author>
<name>Yong Zhao</name>
<email>yong.zhao@amd.com</email>
</author>
<published>2017-09-15T22:20:37Z</published>
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<id>urn:sha1:7bdc53f925af085ffa0580f10489f82b36cc2f1c</id>
<content type='text'>
When max_bytes is not 8 bytes aligned and bo size is larger than
max_bytes, the last 8 bytes in a ttm node may be left unchanged.
For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size
is 0x200000, the problem will happen.

In order to fix the problem, we separately store the max nums of
PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs
structure, rather than inferring it from bytes limit of SDMA
constant fill, i.e. fill_max_bytes.

Together with the fix, we replace the hard code value "10" in
amdgpu_vm_bo_update_mapping() with the corresponding values from
structure amdgpu_vm_pte_funcs.

Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Make SDMA phase quantum configurable</title>
<updated>2017-07-14T15:06:36Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2016-07-15T22:37:05Z</published>
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<id>urn:sha1:a667386cb997a136e169de3cf70f007223bb74ee</id>
<content type='text'>
Set a configurable SDMA phase quantum when enabling SDMA context
switching. The default value significantly reduces SDMA latency
in page table updates when user-mode SDMA queues have concurrent
activity, compared to the initial HW setting.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Andres Rodriguez &lt;andres.rodriguez@amd.com&gt;
Reviewed-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable SDMA context switching for CIK</title>
<updated>2017-07-14T15:06:35Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2016-06-15T20:33:15Z</published>
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<id>urn:sha1:763dbbfa5f678ceec59b81bc13bc9dc445920e9b</id>
<content type='text'>
Enable SDMA context switching on CIK (copied from sdma_v3_0.c).

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v3)</title>
<updated>2017-03-30T03:55:50Z</updated>
<author>
<name>Junwei Zhang</name>
<email>Jerry.Zhang@amd.com</email>
</author>
<published>2017-03-28T08:52:07Z</published>
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<id>urn:sha1:b9be700e38430ee3275cdaf5d1054db83c63d68e</id>
<content type='text'>
v2: fix for all sdma engines
v3: squash in fix for SI/CI

Signed-off-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expand pte flags to uint64_t</title>
<updated>2017-03-30T03:53:38Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2016-09-21T08:19:19Z</published>
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<id>urn:sha1:6b777607c1442857e160a57d02b9951d8e7639b4</id>
<content type='text'>
Necessary for new asics.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
