<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2025-11-14T16:27:29Z</updated>
<entry>
<title>drm/amdgpu: Refactor sriov xgmi topology filling to common code</title>
<updated>2025-11-14T16:27:29Z</updated>
<author>
<name>Will Aitken</name>
<email>wiaitken@amd.com</email>
</author>
<published>2025-09-30T16:24:07Z</published>
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<id>urn:sha1:f1a2cd427d0401c1888c04613fb18d272825a5c2</id>
<content type='text'>
amdgpu_xgmi_fill_topology_info and psp_xgmi_reflect_topology_info
perform the same logic of copying topology info of one node to every
other node in the hive. Instead of having two functions that purport to
do the same thing, this refactoring moves the logic of the fill function
to the reflect function and adds reflecting port number info as well for
complete functionality.

Signed-off-by: Will Aitken &lt;wiaitken@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Avoid xgmi register access</title>
<updated>2025-11-14T16:26:58Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-11-06T08:19:59Z</published>
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<id>urn:sha1:43d08222adf70f6b3ff6ded8dd8e8e4ed3ceff05</id>
<content type='text'>
On single GPU systems, avoid accesses to XGMI link registers.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Check if AID is active before access</title>
<updated>2025-11-12T02:54:18Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-11-06T13:14:29Z</published>
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<id>urn:sha1:baf75a087c41eeb03c471099dc5d77e3b068c33b</id>
<content type='text'>
Access XGMI registers only if AID is active.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add xgmi API to set max speed/width</title>
<updated>2025-06-18T16:19:21Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-06-13T12:31:29Z</published>
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<id>urn:sha1:9750ad5aee4cf24b03dbd3baf475a0840bc0bcea</id>
<content type='text'>
Add an API to set the max possible xgmi speed/width.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Deprecate xgmi_link_speed enum</title>
<updated>2025-06-18T16:19:21Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-06-13T07:03:20Z</published>
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<id>urn:sha1:8c9eb6ce5021adab44b4a365f2ba9bbbfd65f5b5</id>
<content type='text'>
xgmi doesn't have discrete max speeds defined. Speed numbers can be
arbitrary based on SOC. Deprecate the enum.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Use external link order for xgmi data</title>
<updated>2025-05-22T16:02:04Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-05-16T14:46:57Z</published>
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<id>urn:sha1:74956242a0dfe4ef7fef0f9a4e8f7ea7415be97b</id>
<content type='text'>
xgmi_port_num interface reports external link number for port number. To
be consistent, use the external link number for reporting other XGMI
link data also.

v2: For invalid link number return -EINVAL (Kevin)

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Acked-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix query order of XGMI v6.4.1 status</title>
<updated>2025-04-30T22:13:44Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-04-25T07:01:19Z</published>
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<id>urn:sha1:3805e6959ced4c0735a4ae53f0c56324c87c72b2</id>
<content type='text'>
Keep the register offsets as per link order for querying XGMI v6.4.1
link status.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Tested-by: Mangesh Gadre &lt;Mangesh.Gadre@amd.com&gt;
Fixes: 6dee64e765c4 ("drm/amdgpu: Fix xgmi v6.4.1 link status reporting")
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix xgmi v6.4.1 link status reporting</title>
<updated>2025-04-07T19:18:59Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-03-27T04:04:15Z</published>
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<id>urn:sha1:6dee64e765c4c80d128817f519292e249f53a769</id>
<content type='text'>
Use the right register offsets for getting link status.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Parse all deferred errors with UMC aca handle</title>
<updated>2025-03-26T21:44:41Z</updated>
<author>
<name>Xiang Liu</name>
<email>xiang.liu@amd.com</email>
</author>
<published>2025-03-24T09:19:54Z</published>
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<id>urn:sha1:aedc92be9621b31ccc90d79ee7f831944e6bfbef</id>
<content type='text'>
We should only increase the deferred errors in UMC block.

Signed-off-by: Xiang Liu &lt;xiang.liu@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Calculate IP specific xgmi bandwidth</title>
<updated>2025-03-14T03:11:46Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-02-06T12:10:42Z</published>
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<id>urn:sha1:357506799bacb21ba1ed7d64e02ac9c4a1f45b31</id>
<content type='text'>
Use IP version specific xgmi speed/width for bandwidth calculation.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Jonathan Kim &lt;jonathan.kim@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
