<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
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<updated>2019-06-19T06:00:04Z</updated>
<entry>
<title>drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc</title>
<updated>2019-06-19T06:00:04Z</updated>
<author>
<name>Shirish S</name>
<email>shirish.s@amd.com</email>
</author>
<published>2019-06-04T15:55:03Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4a12cc87a815ea7ba857d0e8b34686ce8477834e'/>
<id>urn:sha1:4a12cc87a815ea7ba857d0e8b34686ce8477834e</id>
<content type='text'>
commit 517b91f4cde3043d77b2178548473e8545ef07cb upstream.

[What]
readptr read always returns zero, since most likely
these blocks are either power or clock gated.

[How]
fetch rptr after amdgpu_ring_alloc() which informs
the power management code that the block is about to be
used and hence the gating is turned off.

Signed-off-by: Louis Li &lt;Ching-shih.Li@amd.com&gt;
Signed-off-by: Shirish S &lt;shirish.s@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>drm/amdgpu/vcn:Remove bit 31 for scratch2 to indicate the WA is active</title>
<updated>2018-12-18T22:38:56Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-12-12T19:57:12Z</published>
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<id>urn:sha1:9194fb22ddd8e178e4e83e656b0c2346124ba9ec</id>
<content type='text'>
Remove bit 31 for scratch2 to indicate the Hardware bug work around is active.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn:Scan enc/jpeg fences to init dpg pause new state</title>
<updated>2018-12-18T22:38:49Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-12-12T19:53:12Z</published>
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<id>urn:sha1:12e8b30186b9682dc7e267ab988652b74abfa081</id>
<content type='text'>
Scan enc/jpeg fences to init dpg pause new state in begin use.
It will help set dpg mode to desire state actively.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove messages from IB tests</title>
<updated>2018-11-05T19:21:27Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-10-29T15:12:42Z</published>
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<id>urn:sha1:98079389a873f45ba75bbb20dcf14db0ec694a9a</id>
<content type='text'>
We already print an error message that an IB test failed in the common
code.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: further ring test cleanups</title>
<updated>2018-11-05T19:21:25Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-10-29T09:48:31Z</published>
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<id>urn:sha1:dc9eeff84c77080f545575a30062af0ac65b1eb0</id>
<content type='text'>
Move all error messages from IP specific code into the common helper.
This way we now uses the ring name in the messages instead of the index
and note which device is affected as well.

Also cleanup error handling in the IP specific code and consequently use
ETIMEDOUT when the ring test timed out.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn:Correct VCN cache window definition</title>
<updated>2018-10-09T22:07:39Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-10-02T17:31:31Z</published>
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<id>urn:sha1:825da4d925984de6e1497c2d5e1cbc7b6bbcf07b</id>
<content type='text'>
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn:Replace value with defined macro</title>
<updated>2018-10-09T22:07:33Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-10-02T16:56:32Z</published>
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<id>urn:sha1:b17c524922d65f3ce527277a030d505da3c7b754</id>
<content type='text'>
Replace value with defined macro to make
code more readable

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn:fix dpg pause mode hang issue</title>
<updated>2018-10-09T22:07:26Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-10-02T15:44:50Z</published>
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<id>urn:sha1:2dc4aa523b538f55e38bd4c7b6d704162b5728ac</id>
<content type='text'>
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>BackMerge v4.19-rc6 into drm-next</title>
<updated>2018-10-04T01:03:34Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2018-10-04T01:03:34Z</published>
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<id>urn:sha1:6004f172b375f5747e89afc62ad3baaf1bebd58a</id>
<content type='text'>
I have some pulls based on rc6, and I prefer to have an explicit backmerge.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix vce work queue was not cancelled when suspend</title>
<updated>2018-09-27T15:01:20Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-09-27T12:48:39Z</published>
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<id>urn:sha1:61ea6f5831974ebd1a57baffd7cc30600a2e26fc</id>
<content type='text'>
The vce cancel_delayed_work_sync never be called.
driver call the function in error path.

This caused the A+A suspend hang when runtime pm enebled.
As we will visit the smu in the idle queue. this will cause
smu hang because the dgpu has been suspend, and the dgpu also
will be waked up. As the smu has been hang, so the dgpu resume
will failed.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
</feed>
