<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2025-09-15T20:51:09Z</updated>
<entry>
<title>drm/amdgpu: Remove volatile from RLC files</title>
<updated>2025-09-15T20:51:09Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>siqueira@igalia.com</email>
</author>
<published>2025-09-08T23:15:37Z</published>
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<id>urn:sha1:b8fc541089582ed77cc567bb28a83abe834e8902</id>
<content type='text'>
The RLC uses volatile with some pointers that are not directly related
to any of the situations where volatile is advised to be used [1]. For
this reason, this commit removes all the volatile occurrences associated
with RLC.

1. https://docs.kernel.org/process/volatile-considered-harmful.html

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;siqueira@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Remove volatile from CSB functions</title>
<updated>2025-09-15T20:51:04Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>siqueira@igalia.com</email>
</author>
<published>2025-09-08T23:15:36Z</published>
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<id>urn:sha1:d8586afe38984f9eb98d6753c9b1134295d55ceb</id>
<content type='text'>
The CSB buffer manipulation occurs in memory where the BO is mapped
during initialization, and some references to this buffer are handled
with volatile, which is incorrect in this scenario. There are a few
cases where the use of volatile is accepted, but none of them align with
CSB operations. Therefore, this commit removes all the volatile
variables associated with the CSB code.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;siqueira@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add documentation associated with CSB</title>
<updated>2025-04-30T22:05:41Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>siqueira@igalia.com</email>
</author>
<published>2025-04-21T22:12:26Z</published>
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<id>urn:sha1:ffc7e11c1014db7b2fef4b563a53d444a0932f40</id>
<content type='text'>
Add a description for the get_csb_buffer callback, update the glossary,
and add some extra information about RB, which is associated with CSB
configuration.

Signed-off-by: Rodrigo Siqueira &lt;siqueira@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add rlc TOC header file for soc24</title>
<updated>2024-05-02T20:18:10Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2023-06-28T04:23:58Z</published>
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<id>urn:sha1:00c903563314669af40eddfd68c23e21e40fe8c8</id>
<content type='text'>
Add RLC autoload TOC header file for soc24 ASIC.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new TOC structure</title>
<updated>2024-05-02T20:18:10Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2023-06-28T04:07:40Z</published>
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<id>urn:sha1:e3a911bb3823f010087048af2c933525391627ee</id>
<content type='text'>
Add new RLC_TABLE_OF_CONTENT structure definition.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Update RLC_SPM_MC_CNT by ring wreg in guest</title>
<updated>2024-01-18T20:45:58Z</updated>
<author>
<name>YuanShang</name>
<email>YuanShang.Mao@amd.com</email>
</author>
<published>2024-01-11T14:03:30Z</published>
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<id>urn:sha1:b5387349cadd989f53b3e7b61981859a2c7cc2e6</id>
<content type='text'>
Submit command of wreg in GFX and COMPUTE ring to update
RLC_SPM_MC_CNT in guest machine during runtime.

Signed-off-by: YuanShang &lt;YuanShang.Mao@amd.com&gt;
Reviewed-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)</title>
<updated>2023-07-18T15:16:41Z</updated>
<author>
<name>Victor Lu</name>
<email>victorchengchi.lu@amd.com</email>
</author>
<published>2023-06-16T15:01:59Z</published>
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<id>urn:sha1:8ed49dd1d3a7448744d57e1da2062b074cba2e49</id>
<content type='text'>
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.

v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs
    in amdgpu_mm_wreg_mmio_rlc

v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl

Signed-off-by: Victor Lu &lt;victorchengchi.lu@amd.com&gt;
Reviewed-by: Zhigang Luo &lt;zhigang.luo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add xcc index argument to rlc safe_mode func (v4)</title>
<updated>2023-04-18T20:28:55Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2022-07-27T06:24:05Z</published>
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<id>urn:sha1:86b20703e4c5a3c39891def0a68e7438aeca9db9</id>
<content type='text'>
v1: To support multple XCD case (Le)
v2: unify naming style (Le)
v3: apply the changes to gc v11_0 (Hawking)
v4: apply the changes to gc SOC21 (Morris)

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Morris Zhang &lt;Shiwu.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add helper to init rlc firmware</title>
<updated>2022-09-30T20:59:00Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-09-15T16:21:50Z</published>
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<id>urn:sha1:04fa38cce6e02be4362cd889780d58ec275c4d26</id>
<content type='text'>
To initialzie rlc firmware according to rlc
firmware header version

v2: squash in backwards compat fix

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: add TAP_DELAYS upload support for gfx10</title>
<updated>2022-07-25T13:31:04Z</updated>
<author>
<name>Chengming Gui</name>
<email>Jack.Gui@amd.com</email>
</author>
<published>2022-07-15T05:12:14Z</published>
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<id>urn:sha1:2207efdd8388bd300a0051b1775705d890abd306</id>
<content type='text'>
Support {GLOBAL/SE0/SE1/SE2/SE3}_TAP_DELAYS uploading.

v2: upload TAP_DELAYS before RLC autoload was triggered. (Hawking)

Signed-off-by: Chengming Gui &lt;Jack.Gui@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
