<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2025-06-18T16:19:15Z</updated>
<entry>
<title>drm/amdgpu: fix fence fallback timer expired error</title>
<updated>2025-06-18T16:19:15Z</updated>
<author>
<name>Samuel Zhang</name>
<email>guoqing.zhang@amd.com</email>
</author>
<published>2025-05-08T06:36:35Z</published>
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<id>urn:sha1:4108c2be12ebe78accb40d43f4713a7cc481b18a</id>
<content type='text'>
IH is not working after switching a new gpu index for the first time.

During VM resume, QEMU programming of VF MSIX table (register GFXMSIX_VECT0_ADDR_LO)
may not work.The access could be blocked by nBIF protection as VF isn't in
exclusive access mode. Exclusive access is enabled now, disable/enable MSIX
so that QEMU reprograms MSIX table.

call amdgpu_restore_msix on resume to restore msix table.

Signed-off-by: Samuel Zhang &lt;guoqing.zhang@amd.com&gt;
Acked-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: complement the IH node_id table for multiple AIDs</title>
<updated>2023-06-09T13:43:50Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2022-02-25T07:14:19Z</published>
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<id>urn:sha1:0d81101c190d1835f1bfba85dc3d65b9f9cacd68</id>
<content type='text'>
With different node_id, the SDMA interrupt from multiple AIDs can be
distinguished by sw driver.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add node_id to physical id conversion in EOP handler</title>
<updated>2023-06-09T13:42:13Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2021-11-19T10:03:34Z</published>
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<id>urn:sha1:15091a6f4380a0c1a7202d52e82cdaaf80e2bb70</id>
<content type='text'>
A new field nodeid in interrupt cookie indicates the node ID.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Shiwu Zhang &lt;shiwu.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove pasid_src field from IV entry</title>
<updated>2023-06-09T13:25:47Z</updated>
<author>
<name>Xiaomeng Hou</name>
<email>Xiaomeng.Hou@amd.com</email>
</author>
<published>2023-04-27T05:38:47Z</published>
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<id>urn:sha1:04b3c34f5cb2994a5e466659ea4aa962c0fc09a6</id>
<content type='text'>
PASID_SRC is not actually present in the Interrupt Packet, the field is
taken as reserved bits now. So remove it from IV entry to avoid misuse.

Signed-off-by: Xiaomeng Hou &lt;Xiaomeng.Hou@amd.com&gt;
Reviewed-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: allocate doorbell index for multi-die case</title>
<updated>2023-04-21T12:49:37Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2021-11-19T07:35:30Z</published>
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<id>urn:sha1:47659738fbd2f06730635a487605002ea9b11f3d</id>
<content type='text'>
Allocate different doorbell index for kiq/kcq rings
on each die

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable IH retry CAM on GFX9</title>
<updated>2023-04-13T04:14:08Z</updated>
<author>
<name>Mukul Joshi</name>
<email>mukul.joshi@amd.com</email>
</author>
<published>2023-04-11T20:32:29Z</published>
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<id>urn:sha1:318e431b306e966d2ee99e900a11bdc9a701ee83</id>
<content type='text'>
This patch enables the IH retry CAM on GFX9 series cards. This
retry filter is used to prevent sending lots of retry interrupts
in a short span of time and overflowing the IH ring buffer. This
will also help reduce CPU interrupt workload.

Signed-off-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Convert to Linux IRQ interfaces</title>
<updated>2021-08-10T18:00:44Z</updated>
<author>
<name>Thomas Zimmermann</name>
<email>tzimmermann@suse.de</email>
</author>
<published>2021-08-03T09:06:51Z</published>
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<id>urn:sha1:450d61794d9c1f8839f81d8daf3466b1b52a783a</id>
<content type='text'>
Drop the DRM IRQ midlayer in favor of Linux IRQ interfaces. DRM's
IRQ helpers are mostly useful for UMS drivers. Modern KMS drivers
don't benefit from using it.

DRM IRQ callbacks are now being called directly or inlined.

The interrupt number returned by pci_msi_vector() is now stored
in struct amdgpu_irq. Calls to pci_msi_vector() can fail and return
a negative errno code. Abort initlaizaton in thi case. The DRM IRQ
midlayer does not handle this correctly.

Signed-off-by: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210803090704.32152-2-tzimmermann@suse.de
</content>
</entry>
<entry>
<title>drm/amdgpu: Split amdgpu_device_fini into early and late</title>
<updated>2021-05-20T03:45:49Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2021-05-12T14:26:34Z</published>
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<id>urn:sha1:72c8c97b1522ce7ed1789a42fc9828784ebb5e23</id>
<content type='text'>
Some of the stuff in amdgpu_device_fini such as HW interrupts
disable and pending fences finilization must be done right away on
pci_remove while most of the stuff which relates to finilizing and
releasing driver data structures can be kept until
drm_driver.release hook is called, i.e. when the last device
reference is dropped.

v4: Change functions prefix early-&gt;hw and late-&gt;sw

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210512142648.666476-3-andrey.grodzovsky@amd.com
</content>
</entry>
<entry>
<title>drm/amdgpu: remove irq_src-&gt;data handling</title>
<updated>2021-04-09T20:43:28Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2021-03-19T12:24:03Z</published>
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<id>urn:sha1:266b2d25e3fe741ad8413ce913ef462bfbd823a0</id>
<content type='text'>
That is unused for quite some time now.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add infrastructure for soft IH ring</title>
<updated>2020-11-24T17:06:38Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-10-31T17:38:15Z</published>
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<id>urn:sha1:26f32a377eeddc5af24821b1ef3a3a8de7a80211</id>
<content type='text'>
Add a soft IH ring implementation similar to the hardware IH1/2.

This can be used if the hardware delegation of interrupts to IH1/2
doesn't work for some reason.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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