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<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
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<updated>2018-02-19T19:18:16Z</updated>
<entry>
<title>drm/amdgpu: drop the drm irq pre/post/un install callbacks</title>
<updated>2018-02-19T19:18:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-01-19T00:05:36Z</published>
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<id>urn:sha1:9950cda2a0187314c3cd6a86415ab9050074c5f8</id>
<content type='text'>
The preinstall callback didn't do anything because not all
of the IPs were initialized when it was called.

Move the postinstall setup into sequence in the driver.

The uninstall callback disabled all interrupt source, but
it got called too late in the driver sequence and caused problems
with IPs who already freed the relevant data structures.  Move
the call into the right place in the driver sequence.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Tested-By: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch ih handling to two levels (v3)</title>
<updated>2017-03-30T03:53:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-03-29T22:28:50Z</published>
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<id>urn:sha1:d766e6a393383c60a55bdcc72586f21a1ff12509</id>
<content type='text'>
Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove amdgpu_irq_get_delayed</title>
<updated>2016-11-23T20:08:43Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-11-14T13:25:41Z</published>
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<id>urn:sha1:3b1c9036a678e917c2df6ed12cb96681b7dd92b4</id>
<content type='text'>
Not used any more.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement vi ih check/pre/post_soft_reset</title>
<updated>2016-08-08T15:32:10Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2016-07-18T09:02:57Z</published>
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<id>urn:sha1:1015a1b1750e578868a96d812d388d3c65d7faaf</id>
<content type='text'>
Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add amdgpu_irq_gpu_reset_resume_helper</title>
<updated>2016-07-07T18:54:48Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2016-06-16T08:54:53Z</published>
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<id>urn:sha1:0eaeb070ed6d22e5b42e47210c249283ddf5b08f</id>
<content type='text'>
irq need to update when gpu reset happens.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add irq domain support</title>
<updated>2016-01-11T14:52:57Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-11-06T06:29:08Z</published>
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<id>urn:sha1:5f2323658e4829ffb893553297e64795a90cbcd9</id>
<content type='text'>
Hardware blocks on the GPU like ACP generate interrupts in
the GPU interrupt controller, but are driven by a separate
driver.  Add an irq domain to the GPU driver so that
blocks like ACP can register a Linux interrupt.

Acked-by: Dave Airlie &lt;airlied@redhat.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Implement irq interfaces for CGS</title>
<updated>2015-08-17T20:50:09Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-07-28T18:24:53Z</published>
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<id>urn:sha1:0cf3be21782f8d5b74cce98a2b934e14ef418ef3</id>
<content type='text'>
This implements the irq src registrar.

Reviewed-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add core driver (v4)</title>
<updated>2015-06-04T01:03:15Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-04-20T20:55:21Z</published>
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<id>urn:sha1:d38ceaf99ed015f2a0b9af3499791bd3a3daae21</id>
<content type='text'>
This adds the non-asic specific core driver code.

v2: remove extra kconfig option
v3: implement minor fixes from Fengguang Wu
v4: fix cast in amdgpu_ucode.c

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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