kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c, branch linux-4.17.y

drm/amdgpu: cleanup SA inti and fini(v2)

2018-02-28T19:18:07Z

should use bo_create_kernel instead of split to two function that create and pin the SA bo issue: before this patch, there are DMAR read error in host side when running SRIOV test, the DMAR address dropped in the range of SA bo. fix: after this cleanups of SA init and fini, above DMAR eror gone. v2: keep sa_bo's fini instead of suspend, to keep reporting error Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: adjust timeout for ib_ring_tests(v2)

2018-02-28T19:18:07Z

issue: sometime GFX/MM ib test hit timeout under SRIOV env, root cause is that engine doesn't come back soon enough so the current IB test considered as timed out. fix: for SRIOV GFX IB test wait time need to be expanded a lot during SRIOV runtimei mode since it couldn't really begin before GFX engine come back. for SRIOV MM IB test it always need more time since MM scheduling is not go together with GFX engine, it is controled by h/w MM scheduler so no matter runtime or exclusive mode MM IB test always need more time. v2: use ring type instead of idx to judge Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: cond_exec only for schedule with a job

2018-02-28T19:18:04Z

issue: under SR-IOV sometimes the iB test will fail on gfx ring fix: with cond_exec inserted in RB the gfx engine would skip part packets if RLCV issue PREEMPT on gfx engine if gfx engine is prior to COND_EXEC packet, this is okay for regular command from UMD, but for the ib test since the whole dma format doesn't support PREEMPT so must remove the COND_EXEC from it. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: remove now superflous *_hdp operation

2018-02-19T19:18:22Z

All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by: Christian König Acked-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: fallback to generic HDP operation

2018-02-19T19:18:21Z

When ring special operations aren't available we can fallback to the generic ASIC operations. Signed-off-by: Christian König Acked-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: rename vm_id to vmid

2017-12-27T16:34:02Z

sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: separate VMID and PASID handling

2017-12-27T16:33:52Z

Move both into the new files amdgpu_ids.[ch]. No functional change. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amdgpu: Get rid of dep_sync as a seperate object.

2017-12-06T17:48:31Z

Instead mark fence as explicit in it's amdgpu_sync_entry. v2: Fix use after free bug and add new parameter description. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu:fix world switch hang

2017-07-14T15:06:10Z

for SR-IOV, we must keep the pipeline-sync in the protection of COND_EXEC, otherwise the command consumed by CPG is not consistent when world switch triggerd, e.g.: world switch hit and the IB frame is skipped so the fence won't signal, thus CP will jump to the next DMAframe's pipeline-sync command, and it will make CP hang foever. after pipelin-sync moved into COND_EXEC the consistency can be guaranteed Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: allow flushing VMID0 before IB execution as well

2017-07-14T15:05:57Z

This allows us to queue IBs which needs an up to date system domain as well. Signed-off-by: Christian König Reviewed-by: Alex Deucher Acked-by: Felix Kuehling