<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
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<updated>2018-05-30T06:17:40Z</updated>
<entry>
<title>drm/amdgpu: adjust timeout for ib_ring_tests(v2)</title>
<updated>2018-05-30T06:17:40Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2018-01-23T10:26:20Z</published>
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<id>urn:sha1:f65122de0d3a8f243543108fdd2a0bba7fc02122</id>
<content type='text'>
[ Upstream commit dbf797655a43c6318ebb90b899e6583fcadc6472 ]

issue:
sometime GFX/MM ib test hit timeout under SRIOV env, root cause
is that engine doesn't come back soon enough so the current
IB test considered as timed out.

fix:
for SRIOV GFX IB test wait time need to be expanded a lot during
SRIOV runtimei mode since it couldn't really begin before GFX engine
come back.

for SRIOV MM IB test it always need more time since MM scheduling
is not go together with GFX engine, it is controled by h/w MM
scheduler so no matter runtime or exclusive mode MM IB test
always need more time.

v2:
use ring type instead of idx to judge

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;alexander.levin@microsoft.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename vm_id to vmid</title>
<updated>2017-12-27T16:34:02Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-12-18T16:08:25Z</published>
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<id>urn:sha1:c4f46f22c448ff571eb8fdbe4ab71a25805228d1</id>
<content type='text'>
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: separate VMID and PASID handling</title>
<updated>2017-12-27T16:33:52Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-12-18T15:53:03Z</published>
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<id>urn:sha1:620f774f4687d86c420152309eefb0ef0fcc7e51</id>
<content type='text'>
Move both into the new files amdgpu_ids.[ch]. No functional change.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Get rid of dep_sync as a seperate object.</title>
<updated>2017-12-06T17:48:31Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2017-11-13T19:47:52Z</published>
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<id>urn:sha1:cebb52b7bc325863600aff930407bba773010938</id>
<content type='text'>
Instead mark fence as explicit in it's amdgpu_sync_entry.

v2:
Fix use after free bug and add new parameter description.
Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:fix world switch hang</title>
<updated>2017-07-14T15:06:10Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-06-06T09:25:13Z</published>
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<id>urn:sha1:8fdf074f1840eae838bbccbec37d0a1504ee432b</id>
<content type='text'>
for SR-IOV, we must keep the pipeline-sync in the protection
of COND_EXEC, otherwise the command consumed by CPG is not
consistent when world switch triggerd, e.g.:

world switch hit and the IB frame is skipped so the fence
won't signal, thus CP will jump to the next DMAframe's pipeline-sync
command, and it will make CP hang foever.

after pipelin-sync moved into COND_EXEC the consistency can be
guaranteed

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: allow flushing VMID0 before IB execution as well</title>
<updated>2017-07-14T15:05:57Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-06-28T13:41:17Z</published>
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<id>urn:sha1:df264f9e08081c8c79523fd9e9f5241ed23ee7e8</id>
<content type='text'>
This allows us to queue IBs which needs an up to date system domain as well.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add a ring func for vcn start command</title>
<updated>2017-05-24T21:41:31Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-05-11T20:29:08Z</published>
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<id>urn:sha1:ef44f8541e8e99f1040c0d1b147956e2c2f25d79</id>
<content type='text'>
Needed for the proper command sequence for VCN.

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: make pipeline sync be in same place v2</title>
<updated>2017-05-24T21:40:35Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-05-11T18:52:48Z</published>
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<id>urn:sha1:b9bf33d5ac55aa9f23b60b4d03017b2e59d02f02</id>
<content type='text'>
v2: directly return for 'if' case.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add sched sync for amdgpu job v2</title>
<updated>2017-05-24T21:40:35Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-05-09T07:50:22Z</published>
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<id>urn:sha1:df83d1ebc9e304fa3ba4bf79dba76418789a77cf</id>
<content type='text'>
this is an improvement for previous patch, the sched_sync is to store fence
that could be skipped as scheduled, when job is executed, we didn't need
pipeline_sync if all fences in sched_sync are signalled, otherwise insert
pipeline_sync still.

v2: handle error when adding fence to sync failed.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt; (v1)
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:cleanup flag not used</title>
<updated>2017-05-24T21:40:27Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-05-03T06:55:07Z</published>
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<id>urn:sha1:503bb31be42e3fea15c5e81bb2d84a0123438c85</id>
<content type='text'>
Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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