<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2018-01-30T04:14:30Z</updated>
<entry>
<title>drm/amdgpu: use queue 0 for kiq ring</title>
<updated>2018-01-30T04:14:30Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2017-12-15T01:33:21Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=59fd27cd2fd762b08a1f54de8bbe3b82aba06a13'/>
<id>urn:sha1:59fd27cd2fd762b08a1f54de8bbe3b82aba06a13</id>
<content type='text'>
It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
queue 0.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename amdgpu_wb_* functions</title>
<updated>2017-12-18T15:59:07Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-12-14T21:03:43Z</published>
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<id>urn:sha1:131b4b3686b701079e8fb82eb9384c8acdd3fc72</id>
<content type='text'>
add device for consistency.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: busywait KIQ register accessing (v4)</title>
<updated>2017-10-19T19:27:19Z</updated>
<author>
<name>pding</name>
<email>Pixel.Ding@amd.com</email>
</author>
<published>2017-10-13T07:38:35Z</published>
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<id>urn:sha1:43ca8efa46d9b1c4defa1b27c4dd1ef3866aaad9</id>
<content type='text'>
Register accessing is performed when IRQ is disabled. Never sleep in
this function.

Known issue: dead sleep in many use cases of index/data registers.

v2:
 - wrap polling fence functions.
 - don't trigger IRQ for polling in case of wrongly fence signal.

v3:
 - handle wrap round gracefully.
 - add comments for polling function

v4:
 - don't return negative timeout confused with error code

Signed-off-by: pding &lt;Pixel.Ding@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add option for force enable multipipe policy for compute</title>
<updated>2017-09-28T20:03:21Z</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-09-26T16:22:46Z</published>
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<id>urn:sha1:4a75aefe3feb99ff87c1ea594b4db377b98f50e8</id>
<content type='text'>
Useful for testing the effects of multipipe compute without recompiling.

Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use multipipe compute policy on non PL11 asics</title>
<updated>2017-09-28T20:03:21Z</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-09-26T16:22:45Z</published>
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<id>urn:sha1:0f7607d484f57c31a3e0b5b4e75ff1366cc90b6b</id>
<content type='text'>
A performance regression for OpenCL tests on Polaris11 had this feature
disabled for all asics.

Instead, disable it selectively on the affected asics.

Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/sriov:alloc KIQ MQD in VRAM(v2)</title>
<updated>2017-09-26T19:14:24Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-09-21T07:10:06Z</published>
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<id>urn:sha1:beb841028480a13a664f868688102f3cee762a6b</id>
<content type='text'>
this way after KIQ MQD released in drv unloading, CPC
can still let KIQ access this MQD thus RLCV SAVE_VF
will not fail

v2:
always use VRAM domain for KIQ MQD no matter BM or SRIOV

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx: keep all compute queues on the same pipe</title>
<updated>2017-07-14T15:06:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-07-11T15:11:41Z</published>
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<id>urn:sha1:fd971375411542f9d81111bb081e58727eb09138</id>
<content type='text'>
Spreading them causes performance regressions using compute
queues on Polaris 11.

Cc: Jim Qu &lt;jim.qu@amd.com&gt;
Acked-by: Jim Qu &lt;Jim.Qu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Rename KIQ ring to avoid spaces</title>
<updated>2017-06-15T15:50:27Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2017-06-12T13:05:04Z</published>
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<id>urn:sha1:2119d0db59a428749cc8a6e946f604cf93590c38</id>
<content type='text'>
Swap space for underscore in ring name.

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx: consolidate mqd buffer setup code</title>
<updated>2017-06-07T22:20:59Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-06-07T19:27:52Z</published>
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<id>urn:sha1:b9683c21f69b3d8d7b6741d31a0e3cbf26c7191b</id>
<content type='text'>
It was duplicated across multiple generations.

Reviewed-by: Alex Xie &lt;AlexBin.Xie@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.c</title>
<updated>2017-06-07T22:20:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-06-07T17:31:32Z</published>
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<id>urn:sha1:71c37505e7eaa01fa259debad1a71a7ae061039d</id>
<content type='text'>
Lots more common stuff.

Reviewed-by: Alex Xie &lt;AlexBin.Xie@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
