kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c, branch 0x221E-v0.0-v7.0

drm/amdgpu: Use AMDGPU_MQD_SIZE_ALIGN in KGD

2026-01-29T17:26:55Z

Use AMDGPU_MQD_SIZE_ALIGN for both kernel and user queue. Signed-off-by: Lang Yu Reviewed-by: David Belanger Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher

drm/amdgpu: Avoid excessive dmesg log

2026-01-21T19:25:31Z

KIQ access is not guaranteed to work reliably under all reset situations. Avoid flooding dmesg with HDP flush failure messages. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd: Convert DRM_() to drm_()

2026-01-05T21:59:55Z

The drm_*() macros include the device which is helpful for debugging issues in multi-GPU systems. Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd: Drop amdgpu prefix from message prints

2026-01-05T21:59:55Z

Hardcoding the prefix isn't necessary when using drm_* or dev_* message prints. Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd: Pass `adev` to amdgpu_gfx_parse_disable_cu()

2026-01-05T21:59:54Z

In order for messages to be attribute to the correct device amdgpu_gfx_parse_disable_cu() needs to know what device is being operated on. Pass the argument in. Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amdgpu: fix mes packet params issue when flush hdp.

2025-12-10T22:38:21Z

v4: use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for gfx9 through gfx12. v3: Unify the get_ref_and_mask function in amdgpu_gfx_funcs, to support both GFX11 and earlier generations v2: place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring, since this function only assigns the cp entry. v1: both gfx ring and mes ring use cp0 to flush hdp, cause conflict. use function get_ref_and_mask to assign the cp entry. reassign mes to use cp8 instead. Signed-off-by: chong li Acked-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu/mes: add multi-xcc support

2025-12-08T18:56:29Z

a. extend mes pipe instances to num_xcc * max_mes_pipe b. initialize mes schq/kiq pipes per xcc c. submit mes packet to mes ring according to xcc_id v2: rebase (Alex) Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amd: Remove redundant pm_runtime_mark_last_busy() calls

2025-10-28T15:31:45Z

pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-redundant explicit call to pm_runtime_mark_last_busy(). Acked-by: Alex Deucher Signed-off-by: Sakari Ailus Signed-off-by: Alex Deucher

drm/amdgpu: use GPU_HDP_FLUSH for sriov

2025-10-20T22:25:41Z

Currently SRIOV runtime will use kiq to write HDP_MEM_FLUSH_CNTL for hdp flush. This register need to be write from CPU for nbif to aware, otherwise it will not work. Implement amdgpu_kiq_hdp_flush and use kiq to do gpu hdp flush during sriov runtime. v2: - fallback to amdgpu_asic_flush_hdp when amdgpu_kiq_hdp_flush failed - add function amdgpu_mes_hdp_flush v3: - changed returned error Reviewed-by: Lijo Lazar Signed-off-by: Victor Zhao Signed-off-by: Alex Deucher

drm/amdgpu: Fix for GPU reset being blocked by KIQ I/O.

2025-10-07T18:09:06Z

There is some probability that reset workqueue is blocked by KIQ I/O for 10+ seconds after gpu hangs. So we need to add a in_reset check during each KIQ register poll. Signed-off-by: Heng Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher