<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h, branch 0x221E-v0.0-v7.0</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=0x221E-v0.0-v7.0</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=0x221E-v0.0-v7.0'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2020-08-14T20:22:41Z</updated>
<entry>
<title>drm/amd/pm: optimize the power related source code layout</title>
<updated>2020-08-14T20:22:41Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-08-13T08:39:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e098bc9612c2b60f94920461d71c92962a916e73'/>
<id>urn:sha1:e098bc9612c2b60f94920461d71c92962a916e73</id>
<content type='text'>
The target is to provide a clear entry point(for power routines).
Also this can help to maintain a clear view about the frameworks
used on different ASICs. Hopefully all these can make power part
more friendly to play with.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: put those exposed power interfaces in amdgpu_dpm.c</title>
<updated>2020-08-14T20:22:41Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-08-13T05:37:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e9372d23715d6802fd6d3763cb19c5a0c07ad641'/>
<id>urn:sha1:e9372d23715d6802fd6d3763cb19c5a0c07ad641</id>
<content type='text'>
As other power interfaces.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: optimize i2c bus access implementation</title>
<updated>2020-08-14T20:22:41Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-08-13T03:51:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=20d3c28ce4e28ac4df9d139054aecb65ee5a9ee4'/>
<id>urn:sha1:20d3c28ce4e28ac4df9d139054aecb65ee5a9ee4</id>
<content type='text'>
The caller needs not care about the internal details how the powerplay
API implemented.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: optimize amdgpu_dpm_set_clockgating_by_smu() implementation</title>
<updated>2020-08-14T20:22:41Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-08-12T05:11:24Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b89e9eb681653868e3ecb0287f1cf65aaec853da'/>
<id>urn:sha1:b89e9eb681653868e3ecb0287f1cf65aaec853da</id>
<content type='text'>
Cover the implementation details from outside(of power part).

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: optimize the interface for mgpu fan boost enablement</title>
<updated>2020-08-14T20:22:40Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-08-12T03:53:47Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f10bb940d8d2774fedc63c4dfb975e4310a261cd'/>
<id>urn:sha1:f10bb940d8d2774fedc63c4dfb975e4310a261cd</id>
<content type='text'>
Cover the implementation details from outside(of power). Also preparing
for expanding this to swSMU.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)</title>
<updated>2020-08-06T19:43:56Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-07-23T10:03:35Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=25c933b1c4fcfaa65ed735e9782fdb2622f7b7e8'/>
<id>urn:sha1:25c933b1c4fcfaa65ed735e9782fdb2622f7b7e8</id>
<content type='text'>
A new interface for UMD to retrieve gpu metrics data.

V2: rich the documentation

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move i2c bus lock out of ras structure</title>
<updated>2020-07-21T19:37:40Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-07-17T13:25:38Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=84dd1f698e5fc2b4c1df3ea05371d2fff13c665c'/>
<id>urn:sha1:84dd1f698e5fc2b4c1df3ea05371d2fff13c665c</id>
<content type='text'>
It's not really ras related.  It's just a lock for the
bus in general.  This removes the ras dependency from
the smu i2c bus.

Reviewed-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add SMU mode1 reset</title>
<updated>2020-07-15T16:41:32Z</updated>
<author>
<name>Wenhui Sheng</name>
<email>Wenhui.Sheng@amd.com</email>
</author>
<published>2020-07-10T09:39:24Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ea8139d8d59bd6f014b317e7423345169a56fe49'/>
<id>urn:sha1:ea8139d8d59bd6f014b317e7423345169a56fe49</id>
<content type='text'>
From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.

v2: add mode1 reset dpm interface
v3: change maro name

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Wenhui Sheng &lt;Wenhui.Sheng@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix device attribute node create failed with multi gpu</title>
<updated>2020-05-26T19:51:45Z</updated>
<author>
<name>Kevin Wang</name>
<email>kevin1.wang@amd.com</email>
</author>
<published>2020-05-22T14:06:17Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ba02fd6b1ce5536ad8d052468166dd9eb083c2b9'/>
<id>urn:sha1:ba02fd6b1ce5536ad8d052468166dd9eb083c2b9</id>
<content type='text'>
the origin design will use varible of "attr-&gt;states" to save node
supported states on current gpu device, but for multi gpu device, when
probe second gpu device, the driver will check attribute node states
from previous gpu device wthether to create attribute node.
it will cause other gpu device create attribute node faild.

1. add member attr_list into amdgpu_device to link supported device attribute node.
2. add new structure "struct amdgpu_device_attr_entry{}" to track device attribute state.
3. drop member "states" from amdgpu_device_attr.

v2:
1. move "attr_list" into amdgpu_pm and rename to "pm_attr_list".
2. refine create &amp; remove device node functions parameter.

fix:
drm/amdgpu: optimize amdgpu device attribute code

Signed-off-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add DPM function for XGMI link power down control</title>
<updated>2020-05-14T21:42:27Z</updated>
<author>
<name>John Clements</name>
<email>john.clements@amd.com</email>
</author>
<published>2020-05-13T09:45:57Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5e7067b24fcf1549c72988dd92de6d17ff3d2077'/>
<id>urn:sha1:5e7067b24fcf1549c72988dd92de6d17ff3d2077</id>
<content type='text'>
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
