kernel/drivers/edac/Makefile, branch linux-5.1.y

EDAC, i10nm: Add a driver for Intel 10nm server processors

2019-02-02T12:33:18Z

This driver supports the Intel 10nm series server integrated memory controller. It gets the memory capacity and topology information by reading the registers in PCI configuration space and memory-mapped I/O. It decodes the memory error address to the platform specific address by using the ACPI Address Translation (ADXL) Device Specific Method (DSM). Co-developed-by: Tony Luck Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Cc: James Morse Cc: Mauro Carvalho Chehab Cc: linux-edac Link: https://lkml.kernel.org/r/20190130191519.15393-5-tony.luck@intel.com

EDAC, skx_edac: Delete duplicated code

2019-02-02T12:33:11Z

Delete the duplicated code from skx_edac.c and rename skx_edac.c to skx_base.c. Update the Makefile to build the skx_edac driver from skx_base.c and skx_common.c. Add SPDX to skx_base.c and clean out unnecessary #include lines. [ bp: Drop the license boilerplate - there's an SPDX identifier now. ] Co-developed-by: Tony Luck Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Cc: James Morse Cc: Mauro Carvalho Chehab Cc: linux-edac Link: https://lkml.kernel.org/r/20190130191519.15393-4-tony.luck@intel.com

EDAC, aspeed: Add an Aspeed AST2500 EDAC driver

2019-01-18T14:23:11Z

Add support for the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler Signed-off-by: Borislav Petkov Cc: Andrew Jeffery Cc: Joel Stanley Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-edac Link: https://lkml.kernel.org/r/1547743097-5236-2-git-send-email-schaecsn@gmx.net

drivers: edac: Add EDAC driver support for QCOM SoCs

2018-09-13T20:54:05Z

Add error reporting driver for Single Bit Errors (SBEs) and Double Bit Errors (DBEs). As of now, this driver supports error reporting for Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts are triggered when the errors happen in the cache, the driver handles those interrupts and dumps the syndrome registers. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta Co-developed-by: Venkata Narendra Kumar Gutta Acked-by: Borislav Petkov Signed-off-by: Andy Gross

edac: remove tile driver

2018-03-26T13:56:17Z

The Tile architecture is obsolete and getting removed from the kernel, this driver appears to only be used there, and not on the ARM based successors (Tile-Mx, BlueField), so we should remove it as well. Acked-by: Borislav Petkov Acked-by: Mauro Carvalho Chehab Signed-off-by: Arnd Bergmann

EDAC, ti: Add support for TI keystone and DRA7xx EDAC

2017-11-27T12:51:19Z

TI Keystone and DRA7xx SoCs have support for EDAC on DDR3 memory that can correct one bit errors and detect two bit errors. Add EDAC driver for this feature which plugs into the generic kernel EDAC framework. Signed-off-by: Tero Kristo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac Cc: linux-omap@vger.kernel.org Link: http://lkml.kernel.org/r/1510578490-14510-1-git-send-email-t-kristo@ti.com [ Add SPDX tag and make _emif_get_id() use edac_printk(). ] Signed-off-by: Borislav Petkov

EDAC: Delete edac_stub.c

2017-04-10T15:14:48Z

Move the remaining functionality to edac_mc.c. Convert "edac_report=" to a module parameter. Signed-off-by: Borislav Petkov

EDAC: Remove EDAC_MM_EDAC

2017-04-10T15:14:41Z

Move all the EDAC core functionality behind CONFIG_EDAC and get rid of that indirection. Update defconfigs which had it. While at it, fix dependencies such that EDAC depends on RAS for the tracepoints. Signed-off-by: Borislav Petkov Cc: linux-arm-kernel@lists.infradead.org Cc: linuxppc-dev@lists.ozlabs.org Cc: Chris Metcalf Cc: linux-edac@vger.kernel.org

EDAC, highbank: Align Makefile directives

2017-04-10T15:10:43Z

... like the rest of the file. Signed-off-by: Borislav Petkov

EDAC, thunderx: Add Cavium ThunderX EDAC driver

2017-03-27T09:43:56Z

Add support for Cavium ThunderX EDAC capable on-chip peripherals, namely the DRAM controller (LMC), cache coherent processor interconnect (CCPI) and level 2 cache blocks (L2C-TAD, L2C-MCI, L2C-CBC) Signed-off-by: Sergey Temerkhanov Cc: David.Daney@cavium.com Cc: Jan.Glauber@cavium.com Cc: linux-edac Link: http://lkml.kernel.org/r/20170324222837.60583-1-s.temerkhanov@gmail.com Signed-off-by: Borislav Petkov