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<title>kernel/drivers/dma/xilinx, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
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<updated>2019-03-14T16:11:54Z</updated>
<entry>
<title>Merge tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dma</title>
<updated>2019-03-14T16:11:54Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-03-14T16:11:54Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=31ef489a026ef2c07383ef336dc9b6601c7b9b93'/>
<id>urn:sha1:31ef489a026ef2c07383ef336dc9b6601c7b9b93</id>
<content type='text'>
Pull dmaengine updates from Vinod Koul:

 - dmatest updates for modularizing common struct and code

 - remove SG support for VDMA xilinx IP and updates to driver

 - Update to dw driver to support Intel iDMA controllers multi-block
   support

 - tegra updates for proper reporting of residue

 - Add Snow Ridge ioatdma device id and support for IOATDMA v3.4

 - struct_size() usage and useless LIST_HEAD cleanups in subsystem.

 - qDMA controller driver for Layerscape SoCs

 - stm32-dma PM Runtime support

 - And usual updates to imx-sdma, sprd, Documentation, fsl-edma,
   bcm2835, qcom_hidma etc

* tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (81 commits)
  dmaengine: imx-sdma: fix consistent dma test failures
  dmaengine: imx-sdma: add a test for imx8mq multi sdma devices
  dmaengine: imx-sdma: add clock ratio 1:1 check
  dmaengine: dmatest: move test data alloc &amp; free into functions
  dmaengine: dmatest: add short-hand `buf_size` var in dmatest_func()
  dmaengine: dmatest: wrap src &amp; dst data into a struct
  dmaengine: ioatdma: support latency tolerance report (LTR) for v3.4
  dmaengine: ioatdma: add descriptor pre-fetch support for v3.4
  dmaengine: ioatdma: disable DCA enabling on IOATDMA v3.4
  dmaengine: ioatdma: Add Snow Ridge ioatdma device id
  dmaengine: sprd: Change channel id to slave id for DMA cell specifier
  dt-bindings: dmaengine: sprd: Change channel id to slave id for DMA cell specifier
  dmaengine: mv_xor: Use correct device for DMA API
  Documentation :dmaengine: clarify DMA desc. pointer after submission
  Documentation: dmaengine: fix dmatest.rst warning
  dmaengine: k3dma: Add support for dma-channel-mask
  dmaengine: k3dma: Delete axi_config
  dmaengine: k3dma: Upgrade k3dma driver to support hisi_asp_dma hardware
  Documentation: bindings: dma: Add binding for dma-channel-mask
  Documentation: bindings: k3dma: Extend the k3dma driver binding to support hisi-asp
  ...
</content>
</entry>
<entry>
<title>dmaengine: xilinx_dma: remove set but not used variable 'tail_segment'</title>
<updated>2019-01-20T05:23:29Z</updated>
<author>
<name>YueHaibing</name>
<email>yuehaibing@huawei.com</email>
</author>
<published>2019-01-09T12:10:37Z</published>
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<id>urn:sha1:c2be36ac2141b97f9a35ab560381317566bee357</id>
<content type='text'>
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/dma/xilinx/xilinx_dma.c: In function 'xilinx_vdma_start_transfer':
drivers/dma/xilinx/xilinx_dma.c:1104:33: warning:
 variable 'tail_segment' set but not used [-Wunused-but-set-variable]

It not used since commit b8349172b400 ("dmaengine: xilinx_dma: Drop SG support
for VDMA IP")

Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Reviewed-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>cross-tree: phase out dma_zalloc_coherent()</title>
<updated>2019-01-08T12:58:37Z</updated>
<author>
<name>Luis Chamberlain</name>
<email>mcgrof@kernel.org</email>
</author>
<published>2019-01-04T08:23:09Z</published>
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<id>urn:sha1:750afb08ca71310fcf0c4e2cb1565c63b8235b60</id>
<content type='text'>
We already need to zero out memory for dma_alloc_coherent(), as such
using dma_zalloc_coherent() is superflous. Phase it out.

This change was generated with the following Coccinelle SmPL patch:

@ replace_dma_zalloc_coherent @
expression dev, size, data, handle, flags;
@@

-dma_zalloc_coherent(dev, size, handle, flags)
+dma_alloc_coherent(dev, size, handle, flags)

Suggested-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Luis Chamberlain &lt;mcgrof@kernel.org&gt;
[hch: re-ran the script on the latest tree]
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>dmaengine: xilinx_dma: Drop SG support for VDMA IP</title>
<updated>2019-01-07T04:23:12Z</updated>
<author>
<name>Andrea Merello</name>
<email>andrea.merello@gmail.com</email>
</author>
<published>2018-11-20T15:31:51Z</published>
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<id>urn:sha1:b8349172b4001ea4e8b38a243275aecd90aa7573</id>
<content type='text'>
xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains
conditional code on has_sg variable. has_sg is set only whenever the HW
does support SG mode, that is never true for VDMA IP.

This patch drops the never-taken branches.

Signed-off-by: Andrea Merello &lt;andrea.merello@gmail.com&gt;
Reviewed-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather</title>
<updated>2019-01-07T04:23:12Z</updated>
<author>
<name>Andrea Merello</name>
<email>andrea.merello@gmail.com</email>
</author>
<published>2018-11-20T15:31:49Z</published>
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<id>urn:sha1:05f7ea7f6ef611a077fcbb983fb8d6a99e91e1f6</id>
<content type='text'>
The AXIDMA and CDMA HW can be either direct-access or scatter-gather
version. These are SW incompatible.

The driver can handle both versions: a DT property was used to
tell the driver whether to assume the HW is in scatter-gather mode.

This patch makes the driver to autodetect this information. The DT
property is not required anymore.

No changes for VDMA.

Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Andrea Merello &lt;andrea.merello@gmail.com&gt;
Reviewed-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: xilinx_dma: program hardware supported buffer length</title>
<updated>2019-01-07T04:23:11Z</updated>
<author>
<name>Radhey Shyam Pandey</name>
<email>radhey.shyam.pandey@xilinx.com</email>
</author>
<published>2018-11-20T15:31:48Z</published>
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<id>urn:sha1:ae809690b46a71dc56cda5b3b8884c8c41a0df15</id>
<content type='text'>
AXI-DMA IP supports configurable (c_sg_length_width) buffer length
register width, hence read buffer length (xlnx,sg-length-width) DT
property and ensure that driver doesn't program buffer length
exceeding the supported limit. For VDMA and CDMA there is no change.

Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: devicetree@vger.kernel.org
Signed-off-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Andrea Merello &lt;andrea.merello@gmail.com&gt; [rebase, reword]
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors</title>
<updated>2019-01-07T04:23:11Z</updated>
<author>
<name>Andrea Merello</name>
<email>andrea.merello@gmail.com</email>
</author>
<published>2018-11-20T15:31:46Z</published>
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<id>urn:sha1:5c094d4cac5ba78139f4d7169145b57af7f07981</id>
<content type='text'>
Whenever a single or cyclic transaction is prepared, the driver
could eventually split it over several SG descriptors in order
to deal with the HW maximum transfer length.

This could end up in DMA operations starting from a misaligned
address. This seems fatal for the HW if DRE (Data Realignment Engine)
is not enabled.

This patch eventually adjusts the transfer size in order to make sure
all operations start from an aligned address.

Cc: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Andrea Merello &lt;andrea.merello@gmail.com&gt;
Reviewed-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: xilinx_dma: commonize DMA copy size calculation</title>
<updated>2019-01-07T04:23:11Z</updated>
<author>
<name>Andrea Merello</name>
<email>andrea.merello@gmail.com</email>
</author>
<published>2018-11-20T15:31:45Z</published>
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<id>urn:sha1:616f0f81d857e248a72b5af45ab185196556ae2e</id>
<content type='text'>
This patch removes a bit of duplicated code by introducing a new
function that implements calculations for DMA copy size, and
prepares for changes to the copy size calculation that will
happen in following patches.

Suggested-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Signed-off-by: Andrea Merello &lt;andrea.merello@gmail.com&gt;
Reviewed-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'topic/xilinx' into for-linus</title>
<updated>2018-12-31T14:02:32Z</updated>
<author>
<name>Vinod Koul</name>
<email>vkoul@kernel.org</email>
</author>
<published>2018-12-31T14:02:32Z</published>
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<id>urn:sha1:660611827c03afeb0eec178dc1fb9f842332d908</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dmaengine: zynqmp_dma: replace spin_lock_bh with spin_lock_irqsave</title>
<updated>2018-12-05T09:07:32Z</updated>
<author>
<name>Michael Tretter</name>
<email>m.tretter@pengutronix.de</email>
</author>
<published>2018-11-26T15:14:25Z</published>
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<id>urn:sha1:a5b21a8ba2a0d6ab114b8ca9c8423e84f47844b1</id>
<content type='text'>
All device_prep_dma_* functions and device_issue_pending can be called
from an interrupt context. As this includes hard IRQs, we must use
spin_lock_irqsave() instead of spin_lock_bh() to access chan-&gt;lock.

Signed-off-by: Michael Tretter &lt;m.tretter@pengutronix.de&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
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