kernel/drivers/dma/mediatek/Makefile, branch linux-5.1.yHosts the 0x221E linux distro kernel.https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y2018-11-11T09:45:18Zdmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC2018-11-11T09:45:18ZShun-Chih Yushun-chih.yu@mediatek.com2018-10-18T07:49:11Zurn:sha1:b1f01e48df5a3454b88c5ff1eb4501f685351c67
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu <shun-chih.yu@mediatek.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC2018-03-27T09:48:15ZSean Wangsean.wang@mediatek.com2018-03-15T07:40:36Zurn:sha1:548c4597e984b79aad8190235d664f1c3a433f94
MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has
a single ring is dedicated to memory-to-memory transfer through ring based
descriptor management.
Even though there is only one physical ring available inside HSDMA, the
driver can be easily extended to the support of multiple virtual channels
processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>