<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/crypto/intel, branch linux-6.8.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.8.y</id>
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<updated>2024-05-30T07:49:03Z</updated>
<entry>
<title>crypto: qat - specify firmware files for 402xx</title>
<updated>2024-05-30T07:49:03Z</updated>
<author>
<name>Giovanni Cabiddu</name>
<email>giovanni.cabiddu@intel.com</email>
</author>
<published>2024-04-22T14:13:17Z</published>
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<id>urn:sha1:7017c20186a659fa7d8c67b3a21bc8bb9b674215</id>
<content type='text'>
[ Upstream commit a3dc1f2b6b932a13f139d3be3c765155542c1070 ]

The 4xxx driver can probe 4xxx and 402xx devices. However, the driver
only specifies the firmware images required for 4xxx.
This might result in external tools missing these binaries, if required,
in the initramfs.

Specify the firmware image used by 402xx with the MODULE_FIRMWARE()
macros in the 4xxx driver.

Fixes: a3e8c919b993 ("crypto: qat - add support for 402xx devices")
Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Reviewed-by: Damian Muszynski &lt;damian.muszynski@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: qat - validate slices count returned by FW</title>
<updated>2024-05-30T07:49:01Z</updated>
<author>
<name>Lucas Segarra Fernandez</name>
<email>lucas.segarra.fernandez@intel.com</email>
</author>
<published>2024-04-16T10:33:37Z</published>
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<id>urn:sha1:e57ed345e2e6043629fc74aa5be051415dcc4f77</id>
<content type='text'>
[ Upstream commit 483fd65ce29317044d1d00757e3fd23503b6b04c ]

The function adf_send_admin_tl_start() enables the telemetry (TL)
feature on a QAT device by sending the ICP_QAT_FW_TL_START message to
the firmware. This triggers the FW to start writing TL data to a DMA
buffer in memory and returns an array containing the number of
accelerators of each type (slices) supported by this HW.
The pointer to this array is stored in the adf_tl_hw_data data
structure called slice_cnt.

The array slice_cnt is then used in the function tl_print_dev_data()
to report in debugfs only statistics about the supported accelerators.
An incorrect value of the elements in slice_cnt might lead to an out
of bounds memory read.
At the moment, there isn't an implementation of FW that returns a wrong
value, but for robustness validate the slice count array returned by FW.

Fixes: 69e7649f7cc2 ("crypto: qat - add support for device telemetry")
Signed-off-by: Lucas Segarra Fernandez &lt;lucas.segarra.fernandez@intel.com&gt;
Reviewed-by: Damian Muszynski &lt;damian.muszynski@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: qat - improve error logging to be consistent across features</title>
<updated>2024-05-30T07:49:00Z</updated>
<author>
<name>Adam Guerin</name>
<email>adam.guerin@intel.com</email>
</author>
<published>2024-04-12T12:24:03Z</published>
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<id>urn:sha1:ba22d14028ac371df6473c9a3b0ca867bb73012d</id>
<content type='text'>
[ Upstream commit d281a28bd2a94d72c440457e05a2f04a52f15947 ]

Improve error logging in rate limiting feature. Staying consistent with
the error logging found in the telemetry feature.

Fixes: d9fb8408376e ("crypto: qat - add rate limiting feature to qat_4xxx")
Signed-off-by: Adam Guerin &lt;adam.guerin@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: qat - improve error message in adf_get_arbiter_mapping()</title>
<updated>2024-05-30T07:49:00Z</updated>
<author>
<name>Adam Guerin</name>
<email>adam.guerin@intel.com</email>
</author>
<published>2024-04-12T12:24:02Z</published>
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<id>urn:sha1:463f18973d1fcfa262961b5115e5532def7635e2</id>
<content type='text'>
[ Upstream commit 4a4fc6c0c7fe29f2538013a57ebd7813ec6c12a8 ]

Improve error message to be more readable.

Fixes: 5da6a2d5353e ("crypto: qat - generate dynamically arbiter mappings")
Signed-off-by: Adam Guerin &lt;adam.guerin@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: iaa - Fix async_disable descriptor leak</title>
<updated>2024-04-13T11:10:07Z</updated>
<author>
<name>Tom Zanussi</name>
<email>tom.zanussi@linux.intel.com</email>
</author>
<published>2024-02-25T20:11:33Z</published>
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<content type='text'>
[ Upstream commit 262534ddc88dfea7474ed18adfecf856e4fbe054 ]

The disable_async paths of iaa_compress/decompress() don't free idxd
descriptors in the async_disable case. Currently this only happens in
the testcases where req-&gt;dst is set to null. Add a test to free them
in those paths.

Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: iaa - Fix nr_cpus &lt; nr_iaa case</title>
<updated>2024-04-03T13:32:36Z</updated>
<author>
<name>Tom Zanussi</name>
<email>tom.zanussi@linux.intel.com</email>
</author>
<published>2024-03-21T21:08:45Z</published>
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<content type='text'>
commit 5a7e89d3315d1be86aff8a8bf849023cda6547f7 upstream.

If nr_cpus &lt; nr_iaa, the calculated cpus_per_iaa will be 0, which
causes a divide-by-0 in rebalance_wq_table().

Make sure cpus_per_iaa is 1 in that case, and also in the nr_iaa == 0
case, even though cpus_per_iaa is never used if nr_iaa == 0, for
paranoia.

Cc: &lt;stable@vger.kernel.org&gt; # v6.8+
Reported-by: Jerry Snitselaar &lt;jsnitsel@redhat.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>crypto: qat - resolve race condition during AER recovery</title>
<updated>2024-04-03T13:32:05Z</updated>
<author>
<name>Damian Muszynski</name>
<email>damian.muszynski@intel.com</email>
</author>
<published>2024-02-09T12:43:42Z</published>
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<content type='text'>
[ Upstream commit 7d42e097607c4d246d99225bf2b195b6167a210c ]

During the PCI AER system's error recovery process, the kernel driver
may encounter a race condition with freeing the reset_data structure's
memory. If the device restart will take more than 10 seconds the function
scheduling that restart will exit due to a timeout, and the reset_data
structure will be freed. However, this data structure is used for
completion notification after the restart is completed, which leads
to a UAF bug.

This results in a KFENCE bug notice.

  BUG: KFENCE: use-after-free read in adf_device_reset_worker+0x38/0xa0 [intel_qat]
  Use-after-free read at 0x00000000bc56fddf (in kfence-#142):
  adf_device_reset_worker+0x38/0xa0 [intel_qat]
  process_one_work+0x173/0x340

To resolve this race condition, the memory associated to the container
of the work_struct is freed on the worker if the timeout expired,
otherwise on the function that schedules the worker.
The timeout detection can be done by checking if the caller is
still waiting for completion or not by using completion_done() function.

Fixes: d8cba25d2c68 ("crypto: qat - Intel(R) QAT driver framework")
Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Damian Muszynski &lt;damian.muszynski@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: qat - change SLAs cleanup flow at shutdown</title>
<updated>2024-04-03T13:32:05Z</updated>
<author>
<name>Damian Muszynski</name>
<email>damian.muszynski@intel.com</email>
</author>
<published>2024-02-09T12:42:07Z</published>
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<id>urn:sha1:66d301a867a8570a219d06fd59bbd3191f72f957</id>
<content type='text'>
[ Upstream commit c2304e1a0b8051a60d4eb9c99a1c509d90380ae5 ]

The implementation of the Rate Limiting (RL) feature includes the cleanup
of all SLAs during device shutdown. For each SLA, the firmware is notified
of the removal through an admin message, the data structures that take
into account the budgets are updated and the memory is freed.
However, this explicit cleanup is not necessary as (1) the device is
reset, and the firmware state is lost and (2) all RL data structures
are freed anyway.

In addition, if the device is unresponsive, for example after a PCI
AER error is detected, the admin interface might not be available.
This might slow down the shutdown sequence and cause a timeout in
the recovery flows which in turn makes the driver believe that the
device is not recoverable.

Fix by replacing the explicit SLAs removal with just a free of the
SLA data structures.

Fixes: d9fb8408376e ("crypto: qat - add rate limiting feature to qat_4xxx")
Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Damian Muszynski &lt;damian.muszynski@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: qat - fix ring to service map for dcc in 420xx</title>
<updated>2024-03-26T22:17:12Z</updated>
<author>
<name>Damian Muszynski</name>
<email>damian.muszynski@intel.com</email>
</author>
<published>2024-02-16T17:21:55Z</published>
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<content type='text'>
[ Upstream commit a20a6060e0dd57fecaf55487985aef28bd08c6bf ]

If a device is configured for data compression chaining (dcc), half of the
engines are loaded with the symmetric crypto image and the rest are loaded
with the compression image.
However, in such configuration all rings can handle compression requests.

Fix the ring to service mapping so that when a device is configured for
dcc, the ring to service mapping reports that all rings in a bank can
be used for compression.

Fixes: fcf60f4bcf54 ("crypto: qat - add support for 420xx devices")
Signed-off-by: Damian Muszynski &lt;damian.muszynski@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: qat - fix ring to service map for dcc in 4xxx</title>
<updated>2024-03-26T22:17:12Z</updated>
<author>
<name>Damian Muszynski</name>
<email>damian.muszynski@intel.com</email>
</author>
<published>2024-02-16T17:21:54Z</published>
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<id>urn:sha1:b538b7f7b1829b632fe86883dab816709cbf0b61</id>
<content type='text'>
[ Upstream commit df018f82002a8b4dc407bc9a6f416b9241d14415 ]

If a device is configured for data compression chaining (dcc), half of the
engines are loaded with the symmetric crypto image and the rest are loaded
with the compression image.
However, in such configuration all rings can handle compression requests.

Fix the ring to service mapping so that when a device is configured for
dcc, the ring to service mapping reports that all rings in a bank can
be used for compression.

Fixes: a238487f7965 ("crypto: qat - fix ring to service map for QAT GEN4")
Signed-off-by: Damian Muszynski &lt;damian.muszynski@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
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