<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/crypto/ccp/psp-dev.c, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2026-02-26T22:59:26Z</updated>
<entry>
<title>crypto: ccp - Add an S4 restore flow</title>
<updated>2026-02-26T22:59:26Z</updated>
<author>
<name>Mario Limonciello (AMD)</name>
<email>superm1@kernel.org</email>
</author>
<published>2026-01-16T04:11:30Z</published>
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<id>urn:sha1:10eef0f932387b8595eff9c32e2d5b6f83856f38</id>
<content type='text'>
[ Upstream commit 0ba2035026d0ab6c7c7e65ad8b418dc73d5700d9 ]

The system will have lost power during S4.  The ring used for TEE
communications needs to be initialized before use.

Fixes: f892a21f51162 ("crypto: ccp - use generic power management")
Reported-by: Lars Francke &lt;lars.francke@gmail.com&gt;
Closes: https://lore.kernel.org/platform-driver-x86/CAD-Ua_gfJnQSo8ucS_7ZwzuhoBRJ14zXP7s8b-zX3ZcxcyWePw@mail.gmail.com/
Tested-by: Yijun Shen &lt;Yijun.Shen@Dell.com&gt;
Signed-off-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Reviewed-by: Shyam Sundar S K &lt;Shyam-sundar.S-k@amd.com&gt;
Reviewed-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Link: https://patch.msgid.link/20260116041132.153674-4-superm1@kernel.org
Signed-off-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add AMD Seamless Firmware Servicing (SFS) driver</title>
<updated>2025-09-17T10:17:05Z</updated>
<author>
<name>Ashish Kalra</name>
<email>ashish.kalra@amd.com</email>
</author>
<published>2025-09-16T21:29:49Z</published>
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<id>urn:sha1:648dbccc03a000cd64c2a9d86012d98053545e64</id>
<content type='text'>
AMD Seamless Firmware Servicing (SFS) is a secure method to allow
non-persistent updates to running firmware and settings without
requiring BIOS reflash and/or system reset.

SFS does not address anything that runs on the x86 processors and
it can be used to update ASP firmware, modules, register settings
and update firmware for other microprocessors like TMPM, etc.

SFS driver support adds ioctl support to communicate the SFS
commands to the ASP/PSP by using the TEE mailbox interface.

The Seamless Firmware Servicing (SFS) driver is added as a
PSP sub-device.

For detailed information, please look at the SFS specifications:
https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/58604.pdf

Signed-off-by: Ashish Kalra &lt;ashish.kalra@amd.com&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Reviewed-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Acked-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Link: https://lore.kernel.org/cover.1758057691.git.ashish.kalra@amd.com
</content>
</entry>
<entry>
<title>crypto: ccp - Move message about TSME being enabled later in init</title>
<updated>2024-06-07T11:46:39Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2024-05-28T21:07:12Z</published>
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<id>urn:sha1:059b1352519d1f2f856d80ae6fe11e11891869d2</id>
<content type='text'>
Some of the security attributes data is now populated from an HSTI
command on some processors, so show the message after it has been
populated.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add support for getting security attributes on some older systems</title>
<updated>2024-06-07T11:46:39Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2024-05-28T21:07:11Z</published>
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<id>urn:sha1:82f9327f774c6e040ba63a887a85fa2e290a233a</id>
<content type='text'>
Older systems will not populate the security attributes in the
capabilities register. The PSP on these systems, however, does have a
command to get the security attributes. Use this command during ccp
startup to populate the attributes if they're missing.

Closes: https://github.com/fwupd/fwupd/issues/5284
Closes: https://github.com/fwupd/fwupd/issues/5675
Closes: https://github.com/fwupd/fwupd/issues/6253
Closes: https://github.com/fwupd/fwupd/issues/7280
Closes: https://github.com/fwupd/fwupd/issues/6323
Closes: https://github.com/fwupd/fwupd/discussions/5433
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Move security attributes to their own file</title>
<updated>2024-06-07T11:46:39Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2024-05-28T21:07:09Z</published>
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<id>urn:sha1:56e0d883735002c506e73fa1f1197f3959fc7f0c</id>
<content type='text'>
To prepare for other code that will manipulate security attributes
move the handling code out of sp-pci.c. No intended functional changes.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Represent capabilities register as a union</title>
<updated>2024-06-07T11:46:39Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2024-05-28T21:07:08Z</published>
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<id>urn:sha1:8609dd25f9b271b3338e38b018fd39e49de1e6ca</id>
<content type='text'>
Making the capabilities register a union makes it easier to refer
to the members instead of always doing bit shifts.

No intended functional changes.

Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Suggested-by: Yazen Ghannam &lt;yazen.ghannam@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - State in dmesg that TSME is enabled</title>
<updated>2024-02-17T01:09:16Z</updated>
<author>
<name>Borislav Petkov (AMD)</name>
<email>bp@alien8.de</email>
</author>
<published>2024-02-05T15:46:01Z</published>
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<id>urn:sha1:6e031ef2c201cea07bea3b286ed151378c4099f3</id>
<content type='text'>
In the case when only TSME is enabled, it is useful to state that fact
too, so that users are aware that memory encryption is still enabled
even when the corresponding software variant of memory encryption is not
enabled.

Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Acked-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add support for DBC over PSP mailbox</title>
<updated>2023-09-15T10:29:46Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-09-07T18:48:46Z</published>
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<id>urn:sha1:0470bb1b71ac1f05055b10bdc791953209a7976b</id>
<content type='text'>
On some SOCs DBC is supported through the PSP mailbox instead of
the platform mailbox. This capability is advertised in the PSP
capabilities register. Allow using this communication path if
supported.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add a macro to check capabilities register</title>
<updated>2023-09-15T10:29:46Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-09-07T18:48:45Z</published>
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<id>urn:sha1:3d5845e18066990ede565ffe2975e6d89786da50</id>
<content type='text'>
Offsets are checked by the capabilities register in multiple places.
To make the code more readable add a macro.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add support for extended PSP mailbox commands</title>
<updated>2023-09-15T10:29:45Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-09-07T18:48:43Z</published>
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<id>urn:sha1:6e17375c47a325f79e1f80028344bd4b0bdd985b</id>
<content type='text'>
The PSP mailbox supports a number of extended sub-commands.  These
subcommands are placed in the header of the buffer sent to the mailbox.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
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