kernel/drivers/crypto/ccp/ccp-dev.h, branch linux-5.1.y

crypto: ccp - Validate the the error value used to index error messages

2019-07-26T07:12:53Z

commit 52393d617af7b554f03531e6756facf2ea687d2e upstream. The error code read from the queue status register is only 6 bits wide, but we need to verify its value is within range before indexing the error messages. Fixes: 81422badb3907 ("crypto: ccp - Make syslog errors human-readable") Cc: Reported-by: Cfir Cohen Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman

crypto: ccp - Fix XTS-AES-128 support on v5 CCPs

2017-08-04T01:27:41Z

Version 5 CCPs have some new requirements for XTS-AES: the type field must be specified, and the key requires 512 bits, with each part occupying 256 bits and padded with zeroes. cc: # 4.9.x+ Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

csrypto: ccp - Expand RSA support for a v5 ccp

2017-07-28T09:58:06Z

A version 5 CCP can handle an RSA modulus up to 16k bits. Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Update copyright dates for 2017.

2017-07-28T09:58:01Z

Some updates this year have not had copyright dates changed in modified files. Correct this for 2017. Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - rename ccp driver initialize files as sp device

2017-07-18T10:15:54Z

CCP device initializes is now integerated into higher level SP device, to avoid the confusion lets rename the ccp driver initialization files (ccp-platform.c->sp-platform.c, ccp-pci.c->sp-pci.c). The patch does not make any functional changes other than renaming file and structures Signed-off-by: Brijesh Singh Acked-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Abstract interrupt registeration

2017-07-18T09:57:14Z

The CCP and PSP devices part of AMD Secure Procesor may share the same interrupt. Hence we expand the SP device to register a common interrupt handler and provide functions to CCP and PSP devices to register their interrupt callback which will be invoked upon interrupt. Signed-off-by: Brijesh Singh Acked-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Introduce the AMD Secure Processor device

2017-07-18T09:51:19Z

The CCP device is part of the AMD Secure Processor. In order to expand the usage of the AMD Secure Processor, create a framework that allows functional components of the AMD Secure Processor to be initialized and handled appropriately. Signed-off-by: Brijesh Singh Acked-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Use devres interface to allocate PCI/iomap and cleanup

2017-07-18T09:50:59Z

Update pci and platform files to use devres interface to allocate the PCI and iomap resources. Also add helper functions to consolicate module init, exit and power mangagement code duplication. Signed-off-by: Brijesh Singh Acked-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Add debugfs entries for CCP information

2017-06-19T06:11:47Z

Expose some data about the configuration and operation of the CCP through debugfs entries: device name, capabilities, configuration, statistics. Allow the user to reset the counters to zero by writing (any value) to the 'stats' file. This can be done per queue or per device. Changes from V1: - Correct polarity of test when destroying devices at module unload Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Change ISR handler method for a v3 CCP

2017-04-24T10:11:06Z

The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Cc: # 4.9.x+ Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu