kernel/drivers/crypto/ccp/ccp-dev-v3.c, branch linux-5.1.y

csrypto: ccp - Expand RSA support for a v5 ccp

2017-07-28T09:58:06Z

A version 5 CCP can handle an RSA modulus up to 16k bits. Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Update copyright dates for 2017.

2017-07-28T09:58:01Z

Some updates this year have not had copyright dates changed in modified files. Correct this for 2017. Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Abstract interrupt registeration

2017-07-18T09:57:14Z

The CCP and PSP devices part of AMD Secure Procesor may share the same interrupt. Hence we expand the SP device to register a common interrupt handler and provide functions to CCP and PSP devices to register their interrupt callback which will be invoked upon interrupt. Signed-off-by: Brijesh Singh Acked-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Introduce the AMD Secure Processor device

2017-07-18T09:51:19Z

The CCP device is part of the AMD Secure Processor. In order to expand the usage of the AMD Secure Processor, create a framework that allows functional components of the AMD Secure Processor to be initialized and handled appropriately. Signed-off-by: Brijesh Singh Acked-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Use devres interface to allocate PCI/iomap and cleanup

2017-07-18T09:50:59Z

Update pci and platform files to use devres interface to allocate the PCI and iomap resources. Also add helper functions to consolicate module init, exit and power mangagement code duplication. Signed-off-by: Brijesh Singh Acked-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Change ISR handler method for a v3 CCP

2017-04-24T10:11:06Z

The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Cc: # 4.9.x+ Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Enable 3DES function on v5 CCPs

2017-03-24T14:02:55Z

Wire up support for Triple DES in ECB mode. Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Clean up the LSB slot allocation code

2016-10-25T03:08:23Z

Fix a few problems revealed by testing: verify consistent units, especially in public slot allocation. Percolate some common initialization code up to a common routine. Add some comments. Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - Make syslog errors human-readable

2016-10-02T14:33:45Z

Add human-readable strings to log messages about CCP errors Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu

crypto: ccp - clean up data structure

2016-10-02T14:33:44Z

Change names of data structure instances. Add const keyword where appropriate. Add error handling path. Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu