<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/cpufreq, branch linux-6.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.17.y</id>
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<updated>2025-12-18T12:59:38Z</updated>
<entry>
<title>cpufreq/amd-pstate: Call cppc_set_auto_sel() only for online CPUs</title>
<updated>2025-12-18T12:59:38Z</updated>
<author>
<name>Gautham R. Shenoy</name>
<email>gautham.shenoy@amd.com</email>
</author>
<published>2025-11-07T07:41:45Z</published>
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<id>urn:sha1:a34680a0c5cc86b61d130c1363458d0363edc305</id>
<content type='text'>
[ Upstream commit bb31fef0d03ed17d587b40e3458786be408fb9df ]

amd_pstate_change_mode_without_dvr_change() calls cppc_set_auto_sel()
for all the present CPUs.

However, this callpath eventually calls cppc_set_reg_val() which
accesses the per-cpu cpc_desc_ptr object. This object is initialized
only for online CPUs via acpi_soft_cpu_online() --&gt;
__acpi_processor_start() --&gt; acpi_cppc_processor_probe().

Hence, restrict calling cppc_set_auto_sel() to only the online CPUs.

Fixes: 3ca7bc818d8c ("cpufreq: amd-pstate: Add guided mode control support via sysfs")
Suggested-by: Mario Limonciello (AMD) (kernel.org) &lt;superm1@kernel.org&gt;
Signed-off-by: Gautham R. Shenoy &lt;gautham.shenoy@amd.com&gt;
Signed-off-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Check IDA only before MSR_IA32_PERF_CTL writes</title>
<updated>2025-11-24T09:37:33Z</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2025-11-11T01:08:40Z</published>
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<id>urn:sha1:63e2dfb59b1a8001ba9307b8bd3fb17199428ac0</id>
<content type='text'>
[ Upstream commit 4b747cc628d8f500d56cf1338280eacc66362ff3 ]

Commit ac4e04d9e378 ("cpufreq: intel_pstate: Unchecked MSR aceess in
legacy mode") introduced a check for feature X86_FEATURE_IDA to verify
turbo mode support. Although this is the correct way to check for turbo
mode support, it causes issues on some platforms that disable turbo
during OS boot, but enable it later [1]. Before adding this feature
check, users were able to get turbo mode frequencies by writing 0 to
/sys/devices/system/cpu/intel_pstate/no_turbo post-boot.

To restore the old behavior on the affected systems while still
addressing the unchecked MSR issue on some Skylake-X systems, check
X86_FEATURE_IDA only immediately before updates of MSR_IA32_PERF_CTL
that may involve setting the Turbo Engage Bit (bit 32).

Fixes: ac4e04d9e378 ("cpufreq: intel_pstate: Unchecked MSR aceess in legacy mode")
Reported-by: Aaron Rainbolt &lt;arainbolt@kfocus.org&gt;
Closes: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2122531 [1]
Tested-by: Aaron Rainbolt &lt;arainbolt@kfocus.org&gt;
Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Subject adjustment, changelog edits ]
Link: https://patch.msgid.link/20251111010840.141490-1-srinivas.pandruvada@linux.intel.com
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>cpufreq: tegra186: Initialize all cores to max frequencies</title>
<updated>2025-11-13T20:37:37Z</updated>
<author>
<name>Aaron Kling</name>
<email>webgeek1234@gmail.com</email>
</author>
<published>2025-08-29T02:48:13Z</published>
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<id>urn:sha1:eefea729934f49060542fad2d3eaf8d3301dd5f2</id>
<content type='text'>
[ Upstream commit ba6018929165fc914c665f071f8e8cdbac844a49 ]

During initialization, the EDVD_COREx_VOLT_FREQ registers for some cores
are still at reset values and not reflecting the actual frequency. This
causes get calls to fail. Set all cores to their respective max
frequency during probe to initialize the registers to working values.

Suggested-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Aaron Kling &lt;webgeek1234@gmail.com&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>cpufreq: ondemand: Update the efficient idle check for Intel extended Families</title>
<updated>2025-11-13T20:36:49Z</updated>
<author>
<name>Sohil Mehta</name>
<email>sohil.mehta@intel.com</email>
</author>
<published>2025-09-08T23:06:55Z</published>
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<id>urn:sha1:74986b07dc26eb82ed186c32af3f73c3550136df</id>
<content type='text'>
[ Upstream commit 7f3cfb7943d27a7b61bdac8db739cf0bdc28e87d ]

IO time is considered busy by default for modern Intel processors. The
current check covers recent Family 6 models but excludes the brand new
Families 18 and 19.

According to Arjan van de Ven, the model check was mainly due to a lack
of testing on systems before INTEL_CORE2_MEROM. He suggests considering
all Intel processors as having an efficient idle.

Extend the IO busy classification to all Intel processors starting with
Family 6, including Family 15 (Pentium 4s) and upcoming Families 18/19.

Use an x86 VFM check and move the function to the header file to avoid
using arch-specific #ifdefs in the C file.

Signed-off-by: Sohil Mehta &lt;sohil.mehta@intel.com&gt;
Link: https://patch.msgid.link/20250908230655.2562440-1-sohil.mehta@intel.com
[ rjw: Added empty line after #include ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>cpufreq/longhaul: handle NULL policy in longhaul_exit</title>
<updated>2025-11-13T20:36:47Z</updated>
<author>
<name>Dennis Beier</name>
<email>nanovim@gmail.com</email>
</author>
<published>2025-08-30T14:43:59Z</published>
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<id>urn:sha1:809cf2a7794ca4c14c304b349f4c3ae220701ce4</id>
<content type='text'>
[ Upstream commit 592532a77b736b5153e0c2e4c74aa50af0a352ab ]

longhaul_exit() was calling cpufreq_cpu_get(0) without checking
for a NULL policy pointer. On some systems, this could lead to a
NULL dereference and a kernel warning or panic.

This patch adds a check using unlikely() and returns early if the
policy is NULL.

Bugzilla: #219962

Signed-off-by: Dennis Beier &lt;nanovim@gmail.com&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>cpufreq: ti: Add support for AM62D2</title>
<updated>2025-11-13T20:36:46Z</updated>
<author>
<name>Paresh Bhagat</name>
<email>p-bhagat@ti.com</email>
</author>
<published>2025-08-20T08:33:31Z</published>
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<id>urn:sha1:69a073c6df03dec3aef6510e6bd8ffe10a32fa01</id>
<content type='text'>
[ Upstream commit b5af45302ebc141662b2b60c713c9202e88c943c ]

Add support for TI K3 AM62D2 SoC to read speed and revision values
from hardware and pass to OPP layer. AM62D shares the same configuations
as AM62A so use existing am62a7_soc_data.

Signed-off-by: Paresh Bhagat &lt;p-bhagat@ti.com&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>cpufreq/amd-pstate: Fix a regression leading to EPP 0 after hibernate</title>
<updated>2025-10-29T13:10:18Z</updated>
<author>
<name>Mario Limonciello (AMD)</name>
<email>superm1@kernel.org</email>
</author>
<published>2025-09-23T15:29:29Z</published>
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<id>urn:sha1:5944d1e910f58455a088d5b45f35126698527c65</id>
<content type='text'>
[ Upstream commit 85d7dda5a9f665ea579741ec873a8841f37e8943 ]

After resuming from S4, all CPUs except the boot CPU have the wrong EPP
hint programmed.  This is because when the CPUs were offlined the EPP value
was reset to 0.

This is a similar problem as fixed by
commit ba3319e590571 ("cpufreq/amd-pstate: Fix a regression leading to EPP
0 after resume") and the solution is also similar.  When offlining rather
than reset the values to zero, reset them to match those chosen by the
policy. When the CPUs are onlined again these values will be restored.

Closes: https://community.frame.work/t/increased-power-usage-after-resuming-from-suspend-on-ryzen-7040-kernel-6-15-regression/74531/20?u=mario_limonciello
Fixes: 608a76b65288 ("cpufreq/amd-pstate: Add support for the "Requested CPU Min frequency" BIOS option")
Reviewed-by: Gautham R. Shenoy &lt;gautham.shenoy@amd.com&gt;
Signed-off-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Fix object lifecycle issue in update_qos_request()</title>
<updated>2025-10-19T14:37:24Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2025-09-05T13:52:03Z</published>
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<id>urn:sha1:57e4a6aadf12578b96a038373cffd54b3a58b092</id>
<content type='text'>
commit 69e5d50fcf4093fb3f9f41c4f931f12c2ca8c467 upstream.

The cpufreq_cpu_put() call in update_qos_request() takes place too early
because the latter subsequently calls freq_qos_update_request() that
indirectly accesses the policy object in question through the QoS request
object passed to it.

Fortunately, update_qos_request() is called under intel_pstate_driver_lock,
so this issue does not matter for changing the intel_pstate operation
mode, but it theoretically can cause a crash to occur on CPU device hot
removal (which currently can only happen in virt, but it is formally
supported nevertheless).

Address this issue by modifying update_qos_request() to drop the
reference to the policy later.

Fixes: da5c504c7aae ("cpufreq: intel_pstate: Implement QoS supported freq constraints")
Cc: 5.4+ &lt;stable@vger.kernel.org&gt; # 5.4+
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Reviewed-by: Zihuan Zhang &lt;zhangzihuan@kylinos.cn&gt;
Link: https://patch.msgid.link/2255671.irdbgypaU6@rafael.j.wysocki
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>cpufreq: CPPC: Avoid using CPUFREQ_ETERNAL as transition delay</title>
<updated>2025-10-19T14:37:24Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2025-09-26T10:19:41Z</published>
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<id>urn:sha1:777397e7860a8f7dc654838f0139e32d54f45009</id>
<content type='text'>
commit f965d111e68f4a993cc44d487d416e3d954eea11 upstream.

If cppc_get_transition_latency() returns CPUFREQ_ETERNAL to indicate a
failure to retrieve the transition latency value from the platform
firmware, the CPPC cpufreq driver will use that value (converted to
microseconds) as the policy transition delay, but it is way too large
for any practical use.

Address this by making the driver use the cpufreq's default
transition latency value (in microseconds) as the transition delay
if CPUFREQ_ETERNAL is returned by cppc_get_transition_latency().

Fixes: d4f3388afd48 ("cpufreq / CPPC: Set platform specific transition_delay_us")
Cc: 5.19+ &lt;stable@vger.kernel.org&gt; # 5.19
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Reviewed-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Reviewed-by: Jie Zhan &lt;zhanjie9@hisilicon.com&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Reviewed-by: Qais Yousef &lt;qyousef@layalina.io&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>cpufreq: tegra186: Set target frequency for all cpus in policy</title>
<updated>2025-10-19T14:37:07Z</updated>
<author>
<name>Aaron Kling</name>
<email>webgeek1234@gmail.com</email>
</author>
<published>2025-08-29T02:48:12Z</published>
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<id>urn:sha1:eb639aac99ea6c5c8ed4e6b20ab24145b09c4768</id>
<content type='text'>
[ Upstream commit 0b1bb980fd7cae126ee3d59f817068a13e321b07 ]

The original commit set all cores in a cluster to a shared policy, but
did not update set_target to apply a frequency change to all cores for
the policy. This caused most cores to remain stuck at their boot
frequency.

Fixes: be4ae8c19492 ("cpufreq: tegra186: Share policy per cluster")
Signed-off-by: Aaron Kling &lt;webgeek1234@gmail.com&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
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