<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/cpufreq/intel_pstate.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
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<updated>2024-07-05T07:38:12Z</updated>
<entry>
<title>cpufreq: intel_pstate: Use HWP to initialize ITMT if CPPC is missing</title>
<updated>2024-07-05T07:38:12Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2024-06-20T16:14:53Z</published>
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<id>urn:sha1:08bf4ee1ca75752ab7219581d2ccfe08976b2885</id>
<content type='text'>
commit a1ff59784b277795a613beaa5d3dd9c5595c69a7 upstream.

It is reported that single-thread performance on some hybrid systems
dropped significantly after commit 7feec7430edd ("ACPI: CPPC: Only probe
for _CPC if CPPC v2 is acked") which prevented _CPC from being used if
the support for it had not been confirmed by the platform firmware.

The problem is that if the platform firmware does not confirm CPPC v2
support, cppc_get_perf_caps() returns an error which prevents the
intel_pstate driver from enabling ITMT.  Consequently, the scheduler
does not get any hints on CPU performance differences, so in a hybrid
system some tasks may run on CPUs with lower capacity even though they
should be running on high-capacity CPUs.

To address this, modify intel_pstate to use the information from
MSR_HWP_CAPABILITIES to enable ITMT if CPPC is not available (which is
done already if the highest performance number coming from CPPC is not
realistic).

Fixes: 7feec7430edd ("ACPI: CPPC: Only probe for _CPC if CPPC v2 is acked")
Closes: https://lore.kernel.org/linux-acpi/d01b0a1f-bd33-47fe-ab41-43843d8a374f@kfocus.org
Link: https://lore.kernel.org/linux-acpi/ZnD22b3Br1ng7alf@kf-XE
Reported-by: Aaron Rainbolt &lt;arainbolt@kfocus.org&gt;
Tested-by: Aaron Rainbolt &lt;arainbolt@kfocus.org&gt;
Cc: 5.19+ &lt;stable@vger.kernel.org&gt; # 5.19+
Link: https://patch.msgid.link/12460110.O9o76ZdvQC@rjwysocki.net
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Merge back cpufreq material for 6.9-rc1.</title>
<updated>2024-03-11T14:08:45Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2024-03-11T14:08:45Z</published>
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<id>urn:sha1:e4d0d7f194b929ca0af048bdedb71266c2e75191</id>
<content type='text'>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Update default EPPs for Meteor Lake</title>
<updated>2024-02-24T14:02:33Z</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2024-02-20T02:26:07Z</published>
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<id>urn:sha1:1f4b7fdd71e066aa7c01e3e26ceeb39b47dd5461</id>
<content type='text'>
Update default balanced_performance EPP to 115 and performance EPP to 16.

Changing the balanced_performance EPP has better performance/watt
compared to default powerup EPP value of 128.

Changing the performance EPP to 0x10 shows reduced power for similar
performance as EPP 0. On small form factor devices this is beneficial
as lower power results in lower CPU and skin temperature. This
results in reduced thermal throttling and higher performance.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Allow model specific EPPs</title>
<updated>2024-02-24T14:02:33Z</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2024-02-20T02:26:06Z</published>
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<id>urn:sha1:240a8da623008eb9f4e32c7a19ce16a6605911dc</id>
<content type='text'>
The current implementation allows model specific EPP override for
balanced_performance. Add feature to allow model specific EPP for all
predefined EPP strings. For example for some CPU models, even changing
performance EPP has benefits

Use a mask of EPPs as driver_data instead of just balanced_performance.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: fix pstate limits enforcement for adjust_perf call back</title>
<updated>2024-02-24T14:01:59Z</updated>
<author>
<name>Doug Smythies</name>
<email>dsmythies@telus.net</email>
</author>
<published>2024-02-17T21:30:10Z</published>
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<id>urn:sha1:f0a0fc10abb062d122db5ac4ed42f6d1ca342649</id>
<content type='text'>
There is a loophole in pstate limit clamping for the intel_cpufreq CPU
frequency scaling driver (intel_pstate in passive mode), schedutil CPU
frequency scaling governor, HWP (HardWare Pstate) control enabled, when
the adjust_perf call back path is used.

Fix it.

Fixes: a365ab6b9dfb cpufreq: intel_pstate: Implement the -&gt;adjust_perf() callback
Signed-off-by: Doug Smythies &lt;dsmythies@telus.net&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: remove cpudata::prev_cummulative_iowait</title>
<updated>2024-02-13T12:47:35Z</updated>
<author>
<name>Jiri Slaby (SUSE)</name>
<email>jirislaby@kernel.org</email>
</author>
<published>2024-02-13T11:16:00Z</published>
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<id>urn:sha1:4615ac9010be84d676f9e893e5a7ea4b5febd1e8</id>
<content type='text'>
Commit 09c448d3c61f ("cpufreq: intel_pstate: Use IOWAIT flag in Atom
algorithm") removed the last user of cpudata::prev_cummulative_iowait.
Remove the member too.

Found by https://github.com/jirislaby/clang-struct.

Signed-off-by: Jiri Slaby (SUSE) &lt;jirislaby@kernel.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Refine computation of P-state for given frequency</title>
<updated>2024-01-22T14:18:11Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2024-01-22T14:18:11Z</published>
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<id>urn:sha1:192cdb1c907fd8df2d764c5bb17496e415e59391</id>
<content type='text'>
On systems using HWP, if a given frequency is equal to the maximum turbo
frequency or the maximum non-turbo frequency, the HWP performance level
corresponding to it is already known and can be used directly without
any computation.

Accordingly, adjust the code to use the known HWP performance levels in
the cases mentioned above.

This also helps to avoid limiting CPU capacity artificially in some
cases when the BIOS produces the HWP_CAP numbers using a different
E-core-to-P-core performance scaling factor than expected by the kernel.

Fixes: f5c8cf2a4992 ("cpufreq: intel_pstate: hybrid: Use known scaling factor for P-cores")
Cc: 6.1+ &lt;stable@vger.kernel.org&gt; # 6.1+
Tested-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Update hybrid scaling factor for Meteor Lake</title>
<updated>2024-01-10T14:02:25Z</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2024-01-09T17:48:48Z</published>
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<id>urn:sha1:bde4f5ff8295601554601f78a523d4d97e42433e</id>
<content type='text'>
On some Meteor Lake platforms, maximum one core turbo frequency is not
observed. During hybrid performance to frequency conversion, the maximum
frequency is 100 MHz less. This results in requesting maximum frequency
100 MHz less.

For example when the max one core turbo is 4.9 GHz:
MSR HWP_CAPABILITIES shows highest performance ratio for P-core is 0x3E.
With the current scaling factor of 78741 (1.27x for converting frequency
to performance) results in max frequency of 4.8 GHz. This results in
capping the max scaling frequency as 4.8 GHz, which is 100 MHz less than
the desired.

Add capability to define per CPU model specific scaling factor and define
scaling factor of 80000 (1.25x for converting frequency to performance for
P-cores) for Meteor Lake.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Debug message adjustment, subject edit ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Add Emerald Rapids support in no-HWP mode</title>
<updated>2023-12-19T20:38:09Z</updated>
<author>
<name>Zhenguo Yao</name>
<email>yaozhenguo1@gmail.com</email>
</author>
<published>2023-12-13T10:28:08Z</published>
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<id>urn:sha1:e95013156ad88e6a1e1db6545881f49183e2ee0a</id>
<content type='text'>
Users may disable HWP in firmware, in which case intel_pstate will give up
unless the CPU model is explicitly supported.

See also the following past commits:

 - commit df51f287b5de ("cpufreq: intel_pstate: Add Sapphire Rapids support
   in no-HWP mode")
 - commit d8de7a44e11f ("cpufreq: intel_pstate: Add Skylake servers support")
 - commit 706c5328851d ("cpufreq: intel_pstate: Add Cometlake support in
   no-HWP mode")
 - commit fbdc21e9b038 ("cpufreq: intel_pstate: Add Icelake servers support in
   no-HWP mode")
 - commit 71bb5c82aaae ("cpufreq: intel_pstate: Add Tigerlake support in
   no-HWP mode")

Signed-off-by: Zhenguo Yao &lt;yaozhenguo1@gmail.com&gt;
Acked-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Changelog edits ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Prioritize firmware-provided balance performance EPP</title>
<updated>2023-12-05T20:29:47Z</updated>
<author>
<name>Srinivas Pandruvada</name>
<email>srinivas.pandruvada@linux.intel.com</email>
</author>
<published>2023-11-20T18:59:42Z</published>
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<id>urn:sha1:2719675fa8111a8d7a060133e1dd4797d20c9754</id>
<content type='text'>
The platform firmware can provide a balance performance EPP value by
enabling HWP and programming the EPP to the desired value.

However, currently this only takes effect for processors listed in
intel_epp_balance_perf[], so in order to enable a new processor model
to utilize this mechanism, that table needs to be updated.  It arguably
should not be necessary to modify the kernel to work properly with
every new generation of processors, though, and distributions that don't
always ship the most recent kernels should be able to run reasonably well
on new hardware without code changes.

For this reason, move the check to avoid updating the EPP when the balance
performance EPP is unmodified from the power-up default of 0x80 after the
check that allows the firmware-provided balance performance EPP value to
be retrieved.  This will cause the code to always look for the firmware-
provided value before consulting intel_epp_balance_perf[] and the handling
of new hardware will not depend on whether or not that thable has been
updated yet.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
[ rjw: Subject and changelog edits ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
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