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<title>kernel/drivers/clocksource/riscv_timer.c, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2018-12-18T21:22:23Z</updated>
<entry>
<title>clocksource/drivers/riscv: Change name riscv_timer to timer-riscv</title>
<updated>2018-12-18T21:22:23Z</updated>
<author>
<name>Daniel Lezcano</name>
<email>daniel.lezcano@linaro.org</email>
</author>
<published>2018-12-09T16:34:04Z</published>
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<id>urn:sha1:3d42b32b1d6bdee161f6d629fc850fdf0c0fb2a1</id>
<content type='text'>
In order to unify the names in this directory, let's rename the driver to be
prefixed with timer-*

Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/riscv_timer: Provide the sched_clock</title>
<updated>2018-12-18T21:22:23Z</updated>
<author>
<name>Anup Patel</name>
<email>anup@brainfault.org</email>
</author>
<published>2018-12-04T10:29:52Z</published>
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<id>urn:sha1:92e0d143fdef1faa7560c93fb0d6cd6c61da88ee</id>
<content type='text'>
Currently, we don't have a sched_clock registered for RISC-V systems.
This means Linux time keeping will use jiffies (running at HZ) as the
default sched_clock.

To avoid this, we explicity provide sched_clock using RISC-V rdtime
instruction (similar to riscv_timer clocksource).

Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: Use Linux logical CPU number instead of hartid</title>
<updated>2018-10-23T00:03:37Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2018-10-02T19:15:05Z</published>
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<id>urn:sha1:f99fb607fb2bc0d4ce6b9adb764c65e37f40a92b</id>
<content type='text'>
Setup the cpu_logical_map during boot. Moreover, every SBI call
and PLIC context are based on the physical hartid. Use the logical
CPU to hartid mapping to pass correct hartid to respective functions.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid</title>
<updated>2018-10-23T00:03:36Z</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2018-10-02T19:15:00Z</published>
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<id>urn:sha1:b2f8cfa7ac34202e5fd9551b6507fcd424634c1b</id>
<content type='text'>
It's a bit confusing exactly what this function does: it actually
returns the hartid of an OF processor node, failing with -1 on invalid
nodes.  I've changed the name to _hartid() in order to make that a bit
more clear, as well as adding a comment.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
[Atish: code comment formatting update]
Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>clocksource: new RISC-V SBI timer driver</title>
<updated>2018-08-13T15:31:31Z</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@dabbelt.com</email>
</author>
<published>2018-08-04T08:23:19Z</published>
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<id>urn:sha1:62b0194368147def8c5a77ce604a125d620fc582</id>
<content type='text'>
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems.  The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.

Contains various improvements from Atish Patra &lt;atish.patra@wdc.com&gt;.

Signed-off-by: Dmitriy Cherkasov &lt;dmitriy@oss-tech.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
[hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(),
 minor cleanups, merged  hotplug cpu support and other improvements
 from Atish]
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Acked-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
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