<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/clk/tegra/cvb.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2021-02-11T19:56:05Z</updated>
<entry>
<title>clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param</title>
<updated>2021-02-11T19:56:05Z</updated>
<author>
<name>Lee Jones</name>
<email>lee.jones@linaro.org</email>
</author>
<published>2021-01-26T12:45:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b565eb81276a975bd2d9d28755df1468ef7854e8'/>
<id>urn:sha1:b565eb81276a975bd2d9d28755df1468ef7854e8</id>
<content type='text'>
Fixes the following W=1 kernel build warning(s):

 drivers/clk/tegra/cvb.c:106: warning: Function parameter or member 'align' not described in 'tegra_cvb_add_opp_table'

Cc: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Cc: Prashant Gaikwad &lt;pgaikwad@nvidia.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Cc: Stephen Boyd &lt;sboyd@kernel.org&gt;
Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Cc: Jonathan Hunter &lt;jonathanh@nvidia.com&gt;
Cc: linux-clk@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
Link: https://lore.kernel.org/r/20210126124540.3320214-10-lee.jones@linaro.org
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174</title>
<updated>2019-05-30T18:26:41Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-27T06:55:21Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1802d0beecafe581ad584634ba92f8a471d8a63a'/>
<id>urn:sha1:1802d0beecafe581ad584634ba92f8a471d8a63a</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Richard Fontana &lt;rfontana@redhat.com&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>clk: tegra: dfll: CVB calculation alignment with the regulator</title>
<updated>2019-02-06T13:28:41Z</updated>
<author>
<name>Joseph Lo</name>
<email>josephl@nvidia.com</email>
</author>
<published>2019-01-04T03:06:48Z</published>
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<id>urn:sha1:b3cf8d0695056a370276c416979277635c3e4299</id>
<content type='text'>
The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;"
and "Alex Frid &lt;afrid@nvidia.com&gt;".

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: dfll: improve function-level documentation</title>
<updated>2016-11-02T00:38:50Z</updated>
<author>
<name>Julia Lawall</name>
<email>Julia.Lawall@lip6.fr</email>
</author>
<published>2016-10-01T19:46:29Z</published>
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<id>urn:sha1:42134fa2b70e2b70c600bf87fbe5ea5faa34ad63</id>
<content type='text'>
Adjust variables to correspond to the names used in the parameter list of
the function.  Move the struct device * variable up to the place where it
appears in the parameter list.

Issue detected using Coccinelle (http://coccinelle.lip6.fr/)

Signed-off-by: Julia Lawall &lt;Julia.Lawall@lip6.fr&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: tegra: dfll: Properly clean up on failure and removal</title>
<updated>2016-04-28T10:41:54Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-04-08T13:16:28Z</published>
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<id>urn:sha1:f7c42d98621739d416cc4a739b721574fcbe910c</id>
<content type='text'>
Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also be
cleared upon driver removal.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: dfll: Make code more comprehensible</title>
<updated>2016-04-28T10:41:53Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-04-08T13:09:56Z</published>
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<id>urn:sha1:e8f6a68c508b5d1cc4612ada028d87c74ab279d5</id>
<content type='text'>
Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Unlock top rates for Tegra124 DFLL clock</title>
<updated>2015-09-15T10:54:39Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mikko.perttunen@kapsi.fi</email>
</author>
<published>2015-09-15T09:55:15Z</published>
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<id>urn:sha1:10d9be6ebe9199feb7680433a24b564a31a8f9b1</id>
<content type='text'>
The new determine_rate prototype allows for clock rates exceeding
2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate
instead of round_rate and unlock the top rates supported by the
Tegra124.

Signed-off-by: Mikko Perttunen &lt;mikko.perttunen@kapsi.fi&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Add functions for parsing CVB tables</title>
<updated>2015-07-16T07:32:47Z</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>ttynkkynen@nvidia.com</email>
</author>
<published>2015-05-13T14:58:38Z</published>
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<id>urn:sha1:fa63aa3dea48fd18e560c232424e080a2e2c4779</id>
<content type='text'>
Tegra CVB tables encode the relationship between operating voltage
and optimal frequency as a function of the so-called speedo value.
The speedo value is written to the on-chip fuses at the factory,
which allows the voltage-frequency operating points to be calculated
on an per-chip basis.

Add utility functions to parse the Tegra-specific tables and export the
voltage-frequency pairs to the generic OPP framework for other drivers
to use.

Signed-off-by: Tuomas Tynkkynen &lt;ttynkkynen@nvidia.com&gt;
Signed-off-by: Mikko Perttunen &lt;mikko.perttunen@kapsi.fi&gt;
Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Acked-by: Michael Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
