<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/clk/tegra/clk-periph-gate.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
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<updated>2021-05-31T13:16:46Z</updated>
<entry>
<title>clk: tegra: Don't deassert reset on enabling clocks</title>
<updated>2021-05-31T13:16:46Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-05-16T16:30:40Z</published>
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<id>urn:sha1:4782c0a5dd88e3797426e08c5c437e95a3156631</id>
<content type='text'>
The Tegra clock driver contains legacy code which deasserts hardware reset
when peripheral clocks are enabled. This behaviour comes from a pre-CCF
era of the Tegra drivers. This is unacceptable for modern kernel drivers
which use generic CCF and reset-control APIs because it breaks assumptions
of the drivers about clk/reset sequences and about reset-propagation
delays. Hence remove the awkward legacy behaviour from the clk driver.

In particular PMC driver assumes that hardware blocks remains in reset
while power domain is turning on, but the clk driver deasserts the reset
before power clamp is removed, hence breaking the driver's assumption.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Fix refcounting of gate clocks</title>
<updated>2021-05-31T13:16:24Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-05-16T16:30:34Z</published>
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<id>urn:sha1:c592c8a28f5821e880ac6675781cd8a151b0737c</id>
<content type='text'>
The refcounting of the gate clocks has a bug causing the enable_refcnt
to underflow when unused clocks are disabled. This happens because clk
provider erroneously bumps the refcount if clock is enabled at a boot
time, which it shouldn't be doing, and it does this only for the gate
clocks, while peripheral clocks are using the same gate ops and the
peripheral clocks are missing the initial bump. Hence the refcount of
the peripheral clocks is 0 when unused clocks are disabled and then the
counter is decremented further by the gate ops, causing the integer
underflow.

Fix this problem by removing the erroneous bump and by implementing the
disable_unused() callback, which disables the unused gates properly.

The visible effect of the bug is such that the unused clocks are never
gated if a loaded kernel module grabs the unused clocks and starts to use
them. In practice this shouldn't cause any real problems for the drivers
and boards supported by the kernel today.

Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201</title>
<updated>2019-05-30T18:29:52Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-28T17:10:04Z</published>
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<id>urn:sha1:9952f6918daa4ab5fc81307a9f90e31a4df3b200</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Reviewed-by: Steve Winslow &lt;swinslow@gmail.com&gt;
Reviewed-by: Richard Fontana &lt;rfontana@redhat.com&gt;
Reviewed-by: Alexios Zavras &lt;alexios.zavras@intel.com&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Fix disable unused for clocks sharing enable bit</title>
<updated>2017-03-20T13:13:52Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2017-03-02T13:22:05Z</published>
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<id>urn:sha1:9619dba8325fce098bbc9ee2911d1b0150fec0c9</id>
<content type='text'>
In case 2 clocks share an enable bit and one of them is enabled by a
driver and the other one is not, CCF will think it's enabled because it
will only look at the HW state. Therefore it will disable the clock and
thus also disable the other clock which was enabled. Solve this by
reading the initial state of the enable bit and incrementing the
refcount if it's set.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Constify peripheral clock registers</title>
<updated>2016-04-28T10:41:45Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-20T12:38:39Z</published>
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<id>urn:sha1:7e14f22305b09bd57fc2da3bf2fd3bfd53dc285b</id>
<content type='text'>
The peripheral clock registers are defined in static tables. These
tables never need to be modified at runtime, so they can reside in
read-only memory.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Properly include clk.h</title>
<updated>2015-07-20T18:11:17Z</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2015-06-19T22:00:46Z</published>
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<id>urn:sha1:584ac4e935a1f905d67c8fa3fbe8e32d384721f1</id>
<content type='text'>
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.

Cc: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Move includes to include/soc/tegra</title>
<updated>2014-07-17T11:26:47Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-17T11:17:24Z</published>
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<id>urn:sha1:306a7f9139318a28063282a15b9f9ebacf09c9b9</id>
<content type='text'>
In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: remove legacy reset APIs</title>
<updated>2013-12-11T23:45:07Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-11-06T23:58:16Z</published>
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<id>urn:sha1:2ae77527bb1a510070d039aaa22d1ae9a5807b6f</id>
<content type='text'>
Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: simplify periph clock data</title>
<updated>2013-11-26T16:45:40Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2013-08-22T15:44:06Z</published>
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<id>urn:sha1:d5ff89a82a6d272d210db68a9487877682c94a24</id>
<content type='text'>
This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Workaround for Tegra114 MSENC problem</title>
<updated>2013-04-04T22:10:59Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2013-04-03T14:40:44Z</published>
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<id>urn:sha1:fdcccbd804088eb96881c9f6532de04868f9dbc1</id>
<content type='text'>
Workaround a hardware bug in MSENC during clock enable.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Acked-by: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
</feed>
