<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/clk/sprd/pll.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
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<updated>2020-05-27T03:14:56Z</updated>
<entry>
<title>clk: sprd: return correct type of value for _sprd_pll_recalc_rate</title>
<updated>2020-05-27T03:14:56Z</updated>
<author>
<name>Chunyan Zhang</name>
<email>chunyan.zhang@unisoc.com</email>
</author>
<published>2020-05-19T03:00:36Z</published>
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<id>urn:sha1:c2f30986d418f26abefc2eec90ebf06716c970d2</id>
<content type='text'>
The function _sprd_pll_recalc_rate() defines return value to unsigned
long, but it would return a negative value when malloc fail, changing
to return its parent_rate makes more sense, since if the callback
.recalc_rate() is not set, the framework returns the parent_rate as
well.

Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang &lt;chunyan.zhang@unisoc.com&gt;
Link: https://lkml.kernel.org/r/20200519030036.1785-2-zhang.lyra@gmail.com
Reviewed-by: Baolin Wang &lt;baolin.wang7@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: sprd: fix to get a correct ibias of pll</title>
<updated>2020-04-03T01:07:58Z</updated>
<author>
<name>Chunyan Zhang</name>
<email>chunyan.zhang@unisoc.com</email>
</author>
<published>2020-03-30T02:16:40Z</published>
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<id>urn:sha1:39d1c90665e3ee471b3005780a7df58bb1ba622d</id>
<content type='text'>
The current driver is getting a wrong ibias index of pll clocks from
number 1. This patch fix that issue, then getting ibias index from 0.

Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang &lt;chunyan.zhang@unisoc.com&gt;
Link: https://lkml.kernel.org/r/20200330021640.14133-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: sprd: add missing kfree</title>
<updated>2019-09-18T05:01:02Z</updated>
<author>
<name>Chunyan Zhang</name>
<email>chunyan.zhang@unisoc.com</email>
</author>
<published>2019-09-05T10:30:09Z</published>
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<id>urn:sha1:5e75ea9c67433a065b0e8595ad3c91c7c0ca0d2d</id>
<content type='text'>
The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.

Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang &lt;chunyan.zhang@unisoc.com&gt;
Signed-off-by: Chunyan Zhang &lt;zhang.lyra@gmail.com&gt;
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: sprd: add adjustable pll support</title>
<updated>2017-12-21T23:00:53Z</updated>
<author>
<name>Chunyan Zhang</name>
<email>chunyan.zhang@spreadtrum.com</email>
</author>
<published>2017-12-07T12:57:10Z</published>
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<id>urn:sha1:3e37b005580b9db89d7f335e121d52d3bd58e234</id>
<content type='text'>
Introduced a common adjustable pll clock driver for Spreadtrum SoCs.

Signed-off-by: Chunyan Zhang &lt;chunyan.zhang@spreadtrum.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
