kernel/drivers/clk/spear/clk.h, branch linux-6.9.y

treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 2)

2022-06-10T12:51:35Z

Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Signed-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman

CLK: SPEAr: make structure field and function argument as const

2017-11-02T06:22:32Z

Make the masks field of clk_aux structure const as it do not modify the fields of the aux_clk_masks structure it points to. Make the struct aux_clk_masks *aux argument of the function clk_register_aux as const as the argument is only stored in the masks field of a clk_aux structure which is now made const. Signed-off-by: Bhumika Goyal Acked-by: Viresh Kumar Signed-off-by: Stephen Boyd

Update Viresh Kumar's email address

2015-07-17T23:39:53Z

Switch to my kernel.org alias instead of a badly named gmail address, which I rarely use. Signed-off-by: Viresh Kumar Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

Viresh has moved

2012-06-20T21:39:36Z

viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

SPEAr: clk: Add General Purpose Timer Synthesizer clock

2012-05-12T19:19:27Z

All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from following equations: Fout= Fin/((2 ^ (N+1)) * (M+1)) This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar Reviewed-by: Mike Turquette

SPEAr: clk: Add Fractional Synthesizer clock

2012-05-12T19:19:27Z

All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from following equations: Fout = Fin / (2 * div) (division factor) div is 17 bits:- 0-13 (fractional part) 14-16 (integer part) div is (16-14 bits).(13-0 bits) (in binary) Fout = Fin/(2 * div) Fout = ((Fin / 10000)/(2 * div)) * 10000 Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000 Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000 div << 14 is simply 17 bit value written at register. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar Reviewed-by: Mike Turquette

SPEAr: clk: Add Auxiliary Synthesizer clock

2012-05-12T19:19:26Z

All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on values of eq, x and y. Fout from synthesizer can be given from two equations: Fout1 = (Fin * X/Y)/2 EQ1 Fout2 = Fin * X/Y EQ2 This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar Reviewed-by: Mike Turquette

SPEAr: clk: Add VCO-PLL Synthesizer clock

2012-05-12T19:19:23Z

All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar Reviewed-by: Mike Turquette