kernel/drivers/clk/rockchip, branch linux-6.9.y

clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent

2024-02-27T22:45:53Z

Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires setting high divider value on clk_i2s0_div, and then muxes back to clk_i2s0_frac, clk_i2s0_frac would have no way to change the clk_i2s0_div's divider ratio back to 1 so that it can satisfy the condition for m/n > 20 for fractional division to work correctly. Bug is reproducible by playing 44.1k audio, then 48k audio, and then 44.1k audio again. This results in clk_i2s0_div being set to 49 and clk_i2s0_frac not being able to cope with such a low input clock rate and audio playing extremely slowly. The identical issue is on i2s1 and i2s2 clocks, too. Signed-off-by: Ondrej Jirman Link: https://lore.kernel.org/r/20240217193439.1762213-1-megi@xff.cz Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: use linked clock ID for GATE_LINK

2024-02-27T21:23:06Z

In preparation for properly supporting GATE_LINK switch the unused linked clock argument from the clock's name to its ID. This allows easy and fast lookup of the 'struct clk'. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: fix indent

2024-02-27T21:23:06Z

pclk_mailbox2 is the only RK3588 clock indented with one tab instead of two tabs. Let's fix this. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf

2024-02-27T21:23:06Z

Currently pclk_vo1grf is not exposed, but it should be referenced from the vo1_grf syscon, which needs it enabled. That syscon is required for HDMI RX and TX functionality among other things. Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates and need the VO's hclk enabled in addition to their parent clock. No Fixes tag has been added, since the logic requiring these clocks is not yet upstream anyways. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

Merge branch 'v6.9-shared/clkids' into v6.9-clk/next

2024-02-27T21:17:39Z

clk: rockchip: rk3588: fix CLK_NR_CLKS usage

2024-02-27T16:04:58Z

CLK_NR_CLKS is not part of the DT bindings and needs to be removed from it, just like it recently happened for other platforms. This takes care of it by introducing a new function identifying the maximum used clock ID at runtime. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: rk3568: Add PLL rate for 128MHz

2024-01-25T19:59:43Z

Add PLL rate for 128MHz to allow the panel for the Anbernic RG-ARC series to run at 60hz. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240123212111.202146-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2024-01-12T21:42:35Z

Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...

clk: rockchip: rk3568: Mark pclk_usb as critical

2023-12-05T09:45:55Z

In the reference manual under "2.8.6 NIU Clock gating reliance" it is stated that pclk_usb_niu has a dependency on hclk_usb_niu. While the manual does not state that this is a bi-directional relationship it was noted that the sdmmc2 failed to operate for me in mmc mode if the pclk_usb was not marked as critical. The parent clock of the hclk_sdmmc2 is hclk_usb. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20231204185719.569021-8-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner

clk: rockchip: rk3568: Add PLL rate for 126.4MHz

2023-12-05T09:43:42Z

Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel can run at a requested 60hz. I have confirmed this rate fits with all the constraints listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter 2 Clock & Reset Unit (CRU)." Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner